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| 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
| 2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
| 3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
| 4 // | 4 // |
| 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
| 6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
| 7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
| 8 | 8 |
| 9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
| 10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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| 185 } | 185 } |
| 186 | 186 |
| 187 | 187 |
| 188 #if 0 | 188 #if 0 |
| 189 // Moved to ARM32::AssemblerARM32::and_() | 189 // Moved to ARM32::AssemblerARM32::and_() |
| 190 void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) { | 190 void Assembler::and_(Register rd, Register rn, Operand o, Condition cond) { |
| 191 EmitType01(cond, o.type(), AND, 0, rn, rd, o); | 191 EmitType01(cond, o.type(), AND, 0, rn, rd, o); |
| 192 } | 192 } |
| 193 #endif | 193 #endif |
| 194 | 194 |
| 195 #if 0 |
| 196 // Moved to ARM32::AssemberARM32::eor() |
| 195 void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) { | 197 void Assembler::eor(Register rd, Register rn, Operand o, Condition cond) { |
| 196 EmitType01(cond, o.type(), EOR, 0, rn, rd, o); | 198 EmitType01(cond, o.type(), EOR, 0, rn, rd, o); |
| 197 } | 199 } |
| 198 | 200 |
| 199 #if 0 | |
| 200 // Moved to ARM32::AssemberARM32::sub() | 201 // Moved to ARM32::AssemberARM32::sub() |
| 201 void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) { | 202 void Assembler::sub(Register rd, Register rn, Operand o, Condition cond) { |
| 202 EmitType01(cond, o.type(), SUB, 0, rn, rd, o); | 203 EmitType01(cond, o.type(), SUB, 0, rn, rd, o); |
| 203 } | 204 } |
| 204 #endif | 205 #endif |
| 205 | 206 |
| 206 void Assembler::rsb(Register rd, Register rn, Operand o, Condition cond) { | 207 void Assembler::rsb(Register rd, Register rn, Operand o, Condition cond) { |
| 207 EmitType01(cond, o.type(), RSB, 0, rn, rd, o); | 208 EmitType01(cond, o.type(), RSB, 0, rn, rd, o); |
| 208 } | 209 } |
| 209 | 210 |
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| 3673 | 3674 |
| 3674 | 3675 |
| 3675 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3676 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
| 3676 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3677 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
| 3677 return fpu_reg_names[reg]; | 3678 return fpu_reg_names[reg]; |
| 3678 } | 3679 } |
| 3679 | 3680 |
| 3680 } // namespace dart | 3681 } // namespace dart |
| 3681 | 3682 |
| 3682 #endif // defined TARGET_ARCH_ARM | 3683 #endif // defined TARGET_ARCH_ARM |
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