Subzero: Various fixes in preparation for x86-32 register aliasing.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2118 matching lines @@
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
       Variable *T_1 = nullptr;
       if (Traits::Is64Bit && Dest->getType() == IceType_i64) {
         T_1 = makeReg(IceType_i64);
       } else {
         assert(Dest->getType() != IceType_i64);
         T_1 = makeReg(IceType_i32);
       }
       // cvt() requires its integer argument to be a GPR.
-      T_1->setMustHaveReg();
       Variable *T_2 = makeReg(Dest->getType());
       _cvt(T_1, Src0RM, Traits::Insts::Cvt::Tss2si);
       _mov(T_2, T_1); // T_1 and T_2 may have different integer types
       if (Dest->getType() == IceType_i1)
         _and(T_2, Ctx->getConstantInt1(1));
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Fptoui:
     if (isVectorType(Dest->getType())) {
@@ skipping 28 matching lines @@
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       // t1.i32 = cvt Src0RM; t2.dest_type = t1; Dest = t2.dest_type
       assert(Dest->getType() != IceType_i64);
       Variable *T_1 = nullptr;
       if (Traits::Is64Bit && Dest->getType() == IceType_i32) {
         T_1 = makeReg(IceType_i64);
       } else {
         assert(Dest->getType() != IceType_i32);
         T_1 = makeReg(IceType_i32);
       }
-      T_1->setMustHaveReg();
       Variable *T_2 = makeReg(Dest->getType());
       _cvt(T_1, Src0RM, Traits::Insts::Cvt::Tss2si);
       _mov(T_2, T_1); // T_1 and T_2 may have different integer types
       if (Dest->getType() == IceType_i1)
         _and(T_2, Ctx->getConstantInt1(1));
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Sitofp:
     if (isVectorType(Dest->getType())) {
@@ skipping 21 matching lines @@
       Operand *Src0RM = legalize(Inst->getSrc(0), Legal_Reg | Legal_Mem);
       // Sign-extend the operand.
       // t1.i32 = movsx Src0RM; t2 = Cvt t1.i32; Dest = t2
       Variable *T_1 = nullptr;
       if (Traits::Is64Bit && Src0RM->getType() == IceType_i64) {
         T_1 = makeReg(IceType_i64);
       } else {
         assert(Src0RM->getType() != IceType_i64);
         T_1 = makeReg(IceType_i32);
       }
-      T_1->setMustHaveReg();
       Variable *T_2 = makeReg(Dest->getType());
       if (Src0RM->getType() == T_1->getType())
         _mov(T_1, Src0RM);
       else
         _movsx(T_1, Src0RM);
       _cvt(T_2, T_1, Traits::Insts::Cvt::Si2ss);
       _mov(Dest, T_2);
     }
     break;
   case InstCast::Uitofp: {
@@ skipping 28 matching lines @@
       // Zero-extend the operand.
       // t1.i32 = movzx Src0RM; t2 = Cvt t1.i32; Dest = t2
       Variable *T_1 = nullptr;
       if (Traits::Is64Bit && Src0RM->getType() == IceType_i32) {
         T_1 = makeReg(IceType_i64);
       } else {
         assert(Src0RM->getType() != IceType_i64);
         assert(Traits::Is64Bit || Src0RM->getType() != IceType_i32);
         T_1 = makeReg(IceType_i32);
       }
-      T_1->setMustHaveReg();
       Variable *T_2 = makeReg(Dest->getType());
       if (Src0RM->getType() == T_1->getType())
         _mov(T_1, Src0RM);
       else
         _movzx(T_1, Src0RM);
       _cvt(T_2, T_1, Traits::Insts::Cvt::Si2ss);
       _mov(Dest, T_2);
     }
     break;
   }
@@ skipping 88 matching lines @@
         _mov(DestHi, T_Hi);
       }
     } break;
     case IceType_f64: {
       assert(Src0->getType() == IceType_i64);
       if (Traits::Is64Bit) {
         Operand *Src0RM = legalize(Src0, Legal_Reg | Legal_Mem);
         Variable *T = makeReg(IceType_f64);
         // Movd requires its fp argument (in this case, the bitcast
         // destination) to be an xmm register.
-        T->setMustHaveReg();
         _movd(T, Src0RM);
         _mov(Dest, T);
       } else {
         Src0 = legalize(Src0);
         if (llvm::isa<typename Traits::X86OperandMem>(Src0)) {
           Variable *T = Func->makeVariable(Dest->getType());
           _movq(T, Src0);
           _movq(Dest, T);
           break;
         }
@@ skipping 226 matching lines @@
     Operand *Src1RM = legalize(Src1, Legal_Reg | Legal_Mem);
     Variable *T = nullptr;
     _mov(T, Src0);
     _ucomiss(T, Src1RM);
     if (!HasC2) {
       assert(Traits::TableFcmp[Index].Default);
       _setcc(Dest, Traits::TableFcmp[Index].C1);
       return;
     }
   }
-  Constant *Default = Ctx->getConstantInt32(Traits::TableFcmp[Index].Default);
+  Constant *Default =
+      Ctx->getConstantInt(Dest->getType(), Traits::TableFcmp[Index].Default);
   _mov(Dest, Default);
   if (HasC1) {
     typename Traits::Insts::Label *Label =
         Traits::Insts::Label::create(Func, this);
     _br(Traits::TableFcmp[Index].C1, Label);
     if (HasC2) {
       _br(Traits::TableFcmp[Index].C2, Label);
     }
     Constant *NonDefault =
-        Ctx->getConstantInt32(!Traits::TableFcmp[Index].Default);
+        Ctx->getConstantInt(Dest->getType(), !Traits::TableFcmp[Index].Default);
     _mov_redefined(Dest, NonDefault);
     Context.insert(Label);
   }
 }
 
 inline bool isZero(const Operand *Opnd) {
   if (auto *C64 = llvm::dyn_cast<ConstantInteger64>(Opnd))
     return C64->getValue() == 0;
   if (auto *C32 = llvm::dyn_cast<ConstantInteger32>(Opnd))
     return C32->getValue() == 0;
@@ skipping 156 matching lines @@
   // Legalize the portions of Src0 that are going to be needed.
   if (isZero(Src1)) {
     switch (Condition) {
     default:
       llvm_unreachable("unexpected condition");
       break;
     // These two are not optimized, so we fall through to the general case,
     // which needs the upper and lower halves legalized.
     case InstIcmp::Sgt:
     case InstIcmp::Sle:
-    // These four compare after performing an "or" of the high and low half, so they
-    // need the upper and lower halves legalized.
+    // These four compare after performing an "or" of the high and low half, so
+    // they need the upper and lower halves legalized.
     case InstIcmp::Eq:
     case InstIcmp::Ule:
     case InstIcmp::Ne:
     case InstIcmp::Ugt:
       Src0LoRM = legalize(loOperand(Src0), Legal_Reg | Legal_Mem);
     // These two test only the high half's sign bit, so they need only
     // the upper half legalized.
     case InstIcmp::Sge:
     case InstIcmp::Slt:
       Src0HiRM = legalize(hiOperand(Src0), Legal_Reg | Legal_Mem);
@@ skipping 2345 matching lines @@
       Const = llvm::cast<Constant>(From);
     }
     // There should be no constants of vector type (other than undef).
     assert(!isVectorType(Ty));
 
     // If the operand is a 64 bit constant integer we need to legalize it to a
     // register in x86-64.
     if (Traits::Is64Bit) {
       if (llvm::isa<ConstantInteger64>(Const)) {
         Variable *V = copyToReg(Const, RegNum);
-        V->setMustHaveReg();
         return V;
       }
     }
 
     // If the operand is an 32 bit constant integer, we should check whether we
     // need to randomize it or pool it.
     if (ConstantInteger32 *C = llvm::dyn_cast<ConstantInteger32>(Const)) {
       Operand *NewConst = randomizeOrPoolImmediate(C, RegNum);
       if (NewConst != Const) {
         return NewConst;
@@ skipping 405 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H