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| 1 //===- subzero/src/IceRegAlloc.cpp - Linear-scan implementation -----------===// | 1 //===- subzero/src/IceRegAlloc.cpp - Linear-scan implementation -----------===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 494 VMetadata->getFirstDefinitionSingleBlock(Iter.Cur)) { | 494 VMetadata->getFirstDefinitionSingleBlock(Iter.Cur)) { |
| 495 assert(DefInst->getDest() == Iter.Cur); | 495 assert(DefInst->getDest() == Iter.Cur); |
| 496 bool IsAssign = DefInst->isVarAssign(); | 496 bool IsAssign = DefInst->isVarAssign(); |
| 497 bool IsSingleDef = !VMetadata->isMultiDef(Iter.Cur); | 497 bool IsSingleDef = !VMetadata->isMultiDef(Iter.Cur); |
| 498 FOREACH_VAR_IN_INST(SrcVar, *DefInst) { | 498 FOREACH_VAR_IN_INST(SrcVar, *DefInst) { |
| 499 // Only consider source variables that have (so far) been assigned a | 499 // Only consider source variables that have (so far) been assigned a |
| 500 // register. That register must be one in the RegMask set, e.g. don't | 500 // register. That register must be one in the RegMask set, e.g. don't |
| 501 // try to prefer the stack pointer as a result of the stacksave | 501 // try to prefer the stack pointer as a result of the stacksave |
| 502 // intrinsic. | 502 // intrinsic. |
| 503 if (SrcVar->hasRegTmp()) { | 503 if (SrcVar->hasRegTmp()) { |
| 504 const int32_t SrcReg = SrcVar->getRegNumTmp(); | 504 const llvm::SmallBitVector &Aliases = |
| 505 const bool IsAliasAvailable = | 505 *RegAliases[SrcVar->getRegNumTmp()]; |
| 506 (Iter.RegMask & *RegAliases[SrcReg]).any(); | 506 const int32_t SrcReg = (Iter.RegMask & Aliases).find_first(); |
| 507 const bool IsAliasAvailable = (SrcReg != -1); |
| 507 if (IsAliasAvailable) { | 508 if (IsAliasAvailable) { |
| 508 if (FindOverlap && !Iter.Free[SrcReg]) { | 509 if (FindOverlap && !Iter.Free[SrcReg]) { |
| 509 // Don't bother trying to enable AllowOverlap if the register is | 510 // Don't bother trying to enable AllowOverlap if the register is |
| 510 // already free. | 511 // already free. |
| 511 Iter.AllowOverlap = IsSingleDef && IsAssign && | 512 Iter.AllowOverlap = IsSingleDef && IsAssign && |
| 512 !overlapsDefs(Func, Iter.Cur, SrcVar); | 513 !overlapsDefs(Func, Iter.Cur, SrcVar); |
| 513 } | 514 } |
| 514 if (Iter.AllowOverlap || Iter.Free[SrcReg]) { | 515 if (Iter.AllowOverlap || Iter.Free[SrcReg]) { |
| 515 Iter.Prefer = SrcVar; | 516 Iter.Prefer = SrcVar; |
| 516 Iter.PreferReg = SrcReg; | 517 Iter.PreferReg = SrcReg; |
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| 687 } else { | 688 } else { |
| 688 // Evict all live ranges in Active that register number MinWeightIndex is | 689 // Evict all live ranges in Active that register number MinWeightIndex is |
| 689 // assigned to. | 690 // assigned to. |
| 690 const llvm::SmallBitVector &Aliases = *RegAliases[MinWeightIndex]; | 691 const llvm::SmallBitVector &Aliases = *RegAliases[MinWeightIndex]; |
| 691 for (SizeT I = Active.size(); I > 0; --I) { | 692 for (SizeT I = Active.size(); I > 0; --I) { |
| 692 const SizeT Index = I - 1; | 693 const SizeT Index = I - 1; |
| 693 Variable *Item = Active[Index]; | 694 Variable *Item = Active[Index]; |
| 694 int32_t RegNum = Item->getRegNumTmp(); | 695 int32_t RegNum = Item->getRegNumTmp(); |
| 695 if (Aliases[RegNum]) { | 696 if (Aliases[RegNum]) { |
| 696 dumpLiveRangeTrace("Evicting A ", Item); | 697 dumpLiveRangeTrace("Evicting A ", Item); |
| 697 --RegUses[RegNum]; | 698 const llvm::SmallBitVector &Aliases = *RegAliases[RegNum]; |
| 698 assert(RegUses[RegNum] >= 0); | 699 for (int32_t RegAlias = Aliases.find_first(); RegAlias >= 0; |
| 700 RegAlias = Aliases.find_next(RegAlias)) { |
| 701 --RegUses[RegAlias]; |
| 702 assert(RegUses[RegAlias] >= 0); |
| 703 } |
| 699 Item->setRegNumTmp(Variable::NoRegister); | 704 Item->setRegNumTmp(Variable::NoRegister); |
| 700 moveItem(Active, Index, Handled); | 705 moveItem(Active, Index, Handled); |
| 701 Evicted.push_back(Item); | 706 Evicted.push_back(Item); |
| 702 } | 707 } |
| 703 } | 708 } |
| 704 // Do the same for Inactive. | 709 // Do the same for Inactive. |
| 705 for (SizeT I = Inactive.size(); I > 0; --I) { | 710 for (SizeT I = Inactive.size(); I > 0; --I) { |
| 706 const SizeT Index = I - 1; | 711 const SizeT Index = I - 1; |
| 707 Variable *Item = Inactive[Index]; | 712 Variable *Item = Inactive[Index]; |
| 708 // Note: The Item->rangeOverlaps(Cur) clause is not part of the | 713 // Note: The Item->rangeOverlaps(Cur) clause is not part of the |
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| 979 Str << "\n"; | 984 Str << "\n"; |
| 980 } | 985 } |
| 981 Str << "++++++ Inactive:\n"; | 986 Str << "++++++ Inactive:\n"; |
| 982 for (const Variable *Item : Inactive) { | 987 for (const Variable *Item : Inactive) { |
| 983 dumpLiveRange(Item, Func); | 988 dumpLiveRange(Item, Func); |
| 984 Str << "\n"; | 989 Str << "\n"; |
| 985 } | 990 } |
| 986 } | 991 } |
| 987 | 992 |
| 988 } // end of namespace Ice | 993 } // end of namespace Ice |
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