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Issue 14046006: MIPS: Fix register usage in commit r14239. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 7 years, 8 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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1091 } 1091 }
1092 1092
1093 1093
1094 // Runtime FP routines take up to two double arguments and zero 1094 // Runtime FP routines take up to two double arguments and zero
1095 // or one integer arguments. All are constructed here, 1095 // or one integer arguments. All are constructed here,
1096 // from a0-a3 or f12 and f14. 1096 // from a0-a3 or f12 and f14.
1097 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) { 1097 void Simulator::GetFpArgs(double* x, double* y, int32_t* z) {
1098 if (!IsMipsSoftFloatABI) { 1098 if (!IsMipsSoftFloatABI) {
1099 *x = get_fpu_register_double(12); 1099 *x = get_fpu_register_double(12);
1100 *y = get_fpu_register_double(14); 1100 *y = get_fpu_register_double(14);
1101 *z = registers_[1]; 1101 *z = get_register(a2);
1102 } else { 1102 } else {
1103 // We use a char buffer to get around the strict-aliasing rules which 1103 // We use a char buffer to get around the strict-aliasing rules which
1104 // otherwise allow the compiler to optimize away the copy. 1104 // otherwise allow the compiler to optimize away the copy.
1105 char buffer[sizeof(*x)]; 1105 char buffer[sizeof(*x)];
1106 int32_t* reg_buffer = reinterpret_cast<int32_t*>(buffer); 1106 int32_t* reg_buffer = reinterpret_cast<int32_t*>(buffer);
1107 1107
1108 // Registers a0 and a1 -> x. 1108 // Registers a0 and a1 -> x.
1109 reg_buffer[0] = get_register(a0); 1109 reg_buffer[0] = get_register(a0);
1110 reg_buffer[1] = get_register(a1); 1110 reg_buffer[1] = get_register(a1);
1111 memcpy(x, buffer, sizeof(buffer)); 1111 memcpy(x, buffer, sizeof(buffer));
1112 // Registers a2 and a3 -> y. 1112 // Registers a2 and a3 -> y.
1113 reg_buffer[0] = get_register(a2); 1113 reg_buffer[0] = get_register(a2);
1114 reg_buffer[1] = get_register(a3); 1114 reg_buffer[1] = get_register(a3);
1115 memcpy(y, buffer, sizeof(buffer)); 1115 memcpy(y, buffer, sizeof(buffer));
1116 // Register 2 -> z. 1116 // Register 2 -> z.
1117 memcpy(buffer, registers_ + 2, sizeof(*z)); 1117 reg_buffer[0] = get_register(a2);
1118 memcpy(z, buffer, sizeof(*z)); 1118 memcpy(z, buffer, sizeof(*z));
1119
1120 // Register 2 -> y.
1121 reg_buffer[0] = get_register(a2);
1122 memcpy(y, buffer, sizeof(*y));
1123 } 1119 }
1124 } 1120 }
1125 1121
1126 1122
1127 // The return value is either in v0/v1 or f0. 1123 // The return value is either in v0/v1 or f0.
1128 void Simulator::SetFpResult(const double& result) { 1124 void Simulator::SetFpResult(const double& result) {
1129 if (!IsMipsSoftFloatABI) { 1125 if (!IsMipsSoftFloatABI) {
1130 set_fpu_register_double(0, result); 1126 set_fpu_register_double(0, result);
1131 } else { 1127 } else {
1132 char buffer[2 * sizeof(registers_[0])]; 1128 char buffer[2 * sizeof(registers_[0])];
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2903 } 2899 }
2904 2900
2905 2901
2906 #undef UNSUPPORTED 2902 #undef UNSUPPORTED
2907 2903
2908 } } // namespace v8::internal 2904 } } // namespace v8::internal
2909 2905
2910 #endif // USE_SIMULATOR 2906 #endif // USE_SIMULATOR
2911 2907
2912 #endif // V8_TARGET_ARCH_MIPS 2908 #endif // V8_TARGET_ARCH_MIPS
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