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Side by Side Diff: src/mips64/simulator-mips64.cc

Issue 1402923002: MIPS: Fix mina in mips32 and mips64 simulator (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 2 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS64 10 #if V8_TARGET_ARCH_MIPS64
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2474 set_fpu_register_float(fd_reg(), ft); 2474 set_fpu_register_float(fd_reg(), ft);
2475 } else if (!std::isnan(fs) && std::isnan(ft)) { 2475 } else if (!std::isnan(fs) && std::isnan(ft)) {
2476 set_fpu_register_float(fd_reg(), fs); 2476 set_fpu_register_float(fd_reg(), fs);
2477 } else { 2477 } else {
2478 float result; 2478 float result;
2479 if (fabs(fs) > fabs(ft)) { 2479 if (fabs(fs) > fabs(ft)) {
2480 result = ft; 2480 result = ft;
2481 } else if (fabs(fs) < fabs(ft)) { 2481 } else if (fabs(fs) < fabs(ft)) {
2482 result = fs; 2482 result = fs;
2483 } else { 2483 } else {
2484 result = (fs > ft ? fs : ft); 2484 result = (fs < ft ? fs : ft);
2485 } 2485 }
2486 set_fpu_register_float(fd_reg(), result); 2486 set_fpu_register_float(fd_reg(), result);
2487 } 2487 }
2488 break; 2488 break;
2489 case MAXA: 2489 case MAXA:
2490 DCHECK(kArchVariant == kMips64r6); 2490 DCHECK(kArchVariant == kMips64r6);
2491 fs = get_fpu_register_float(fs_reg()); 2491 fs = get_fpu_register_float(fs_reg());
2492 if (std::isnan(fs) && std::isnan(ft)) { 2492 if (std::isnan(fs) && std::isnan(ft)) {
2493 set_fpu_register_float(fd_reg(), fs); 2493 set_fpu_register_float(fd_reg(), fs);
2494 } else if (std::isnan(fs) && !std::isnan(ft)) { 2494 } else if (std::isnan(fs) && !std::isnan(ft)) {
(...skipping 188 matching lines...) Expand 10 before | Expand all | Expand 10 after
2683 set_fpu_register_double(fd_reg(), ft); 2683 set_fpu_register_double(fd_reg(), ft);
2684 } else if (!std::isnan(fs) && std::isnan(ft)) { 2684 } else if (!std::isnan(fs) && std::isnan(ft)) {
2685 set_fpu_register_double(fd_reg(), fs); 2685 set_fpu_register_double(fd_reg(), fs);
2686 } else { 2686 } else {
2687 double result; 2687 double result;
2688 if (fabs(fs) > fabs(ft)) { 2688 if (fabs(fs) > fabs(ft)) {
2689 result = ft; 2689 result = ft;
2690 } else if (fabs(fs) < fabs(ft)) { 2690 } else if (fabs(fs) < fabs(ft)) {
2691 result = fs; 2691 result = fs;
2692 } else { 2692 } else {
2693 result = (fs > ft ? fs : ft); 2693 result = (fs < ft ? fs : ft);
2694 } 2694 }
2695 set_fpu_register_double(fd_reg(), result); 2695 set_fpu_register_double(fd_reg(), result);
2696 } 2696 }
2697 break; 2697 break;
2698 case MAXA: 2698 case MAXA:
2699 DCHECK(kArchVariant == kMips64r6); 2699 DCHECK(kArchVariant == kMips64r6);
2700 fs = get_fpu_register_double(fs_reg()); 2700 fs = get_fpu_register_double(fs_reg());
2701 if (std::isnan(fs) && std::isnan(ft)) { 2701 if (std::isnan(fs) && std::isnan(ft)) {
2702 set_fpu_register_double(fd_reg(), fs); 2702 set_fpu_register_double(fd_reg(), fs);
2703 } else if (std::isnan(fs) && !std::isnan(ft)) { 2703 } else if (std::isnan(fs) && !std::isnan(ft)) {
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4495 } 4495 }
4496 4496
4497 4497
4498 #undef UNSUPPORTED 4498 #undef UNSUPPORTED
4499 } // namespace internal 4499 } // namespace internal
4500 } // namespace v8 4500 } // namespace v8
4501 4501
4502 #endif // USE_SIMULATOR 4502 #endif // USE_SIMULATOR
4503 4503
4504 #endif // V8_TARGET_ARCH_MIPS64 4504 #endif // V8_TARGET_ARCH_MIPS64
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