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Issue 1402923002: MIPS: Fix mina in mips32 and mips64 simulator (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 2 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include <limits.h> 5 #include <limits.h>
6 #include <stdarg.h> 6 #include <stdarg.h>
7 #include <stdlib.h> 7 #include <stdlib.h>
8 #include <cmath> 8 #include <cmath>
9 9
10 #if V8_TARGET_ARCH_MIPS 10 #if V8_TARGET_ARCH_MIPS
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2303 set_fpu_register_double(fd_reg(), ft); 2303 set_fpu_register_double(fd_reg(), ft);
2304 } else if (!std::isnan(fs) && std::isnan(ft)) { 2304 } else if (!std::isnan(fs) && std::isnan(ft)) {
2305 set_fpu_register_double(fd_reg(), fs); 2305 set_fpu_register_double(fd_reg(), fs);
2306 } else { 2306 } else {
2307 double result; 2307 double result;
2308 if (fabs(fs) > fabs(ft)) { 2308 if (fabs(fs) > fabs(ft)) {
2309 result = ft; 2309 result = ft;
2310 } else if (fabs(fs) < fabs(ft)) { 2310 } else if (fabs(fs) < fabs(ft)) {
2311 result = fs; 2311 result = fs;
2312 } else { 2312 } else {
2313 result = (fs > ft ? fs : ft); 2313 result = (fs < ft ? fs : ft);
2314 } 2314 }
2315 set_fpu_register_double(fd_reg(), result); 2315 set_fpu_register_double(fd_reg(), result);
2316 } 2316 }
2317 break; 2317 break;
2318 case MAXA: 2318 case MAXA:
2319 DCHECK(IsMipsArchVariant(kMips32r6)); 2319 DCHECK(IsMipsArchVariant(kMips32r6));
2320 fs = get_fpu_register_double(fs_reg()); 2320 fs = get_fpu_register_double(fs_reg());
2321 if (std::isnan(fs) && std::isnan(ft)) { 2321 if (std::isnan(fs) && std::isnan(ft)) {
2322 set_fpu_register_double(fd_reg(), fs); 2322 set_fpu_register_double(fd_reg(), fs);
2323 } else if (std::isnan(fs) && !std::isnan(ft)) { 2323 } else if (std::isnan(fs) && !std::isnan(ft)) {
(...skipping 739 matching lines...) Expand 10 before | Expand all | Expand 10 after
3063 set_fpu_register_float(fd_reg(), ft); 3063 set_fpu_register_float(fd_reg(), ft);
3064 } else if (!std::isnan(fs) && std::isnan(ft)) { 3064 } else if (!std::isnan(fs) && std::isnan(ft)) {
3065 set_fpu_register_float(fd_reg(), fs); 3065 set_fpu_register_float(fd_reg(), fs);
3066 } else { 3066 } else {
3067 float result; 3067 float result;
3068 if (fabs(fs) > fabs(ft)) { 3068 if (fabs(fs) > fabs(ft)) {
3069 result = ft; 3069 result = ft;
3070 } else if (fabs(fs) < fabs(ft)) { 3070 } else if (fabs(fs) < fabs(ft)) {
3071 result = fs; 3071 result = fs;
3072 } else { 3072 } else {
3073 result = (fs > ft ? fs : ft); 3073 result = (fs < ft ? fs : ft);
3074 } 3074 }
3075 set_fpu_register_float(fd_reg(), result); 3075 set_fpu_register_float(fd_reg(), result);
3076 } 3076 }
3077 break; 3077 break;
3078 case MAXA: 3078 case MAXA:
3079 DCHECK(IsMipsArchVariant(kMips32r6)); 3079 DCHECK(IsMipsArchVariant(kMips32r6));
3080 fs = get_fpu_register_float(fs_reg()); 3080 fs = get_fpu_register_float(fs_reg());
3081 if (std::isnan(fs) && std::isnan(ft)) { 3081 if (std::isnan(fs) && std::isnan(ft)) {
3082 set_fpu_register_float(fd_reg(), fs); 3082 set_fpu_register_float(fd_reg(), fs);
3083 } else if (std::isnan(fs) && !std::isnan(ft)) { 3083 } else if (std::isnan(fs) && !std::isnan(ft)) {
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4335 4335
4336 4336
4337 #undef UNSUPPORTED 4337 #undef UNSUPPORTED
4338 4338
4339 } // namespace internal 4339 } // namespace internal
4340 } // namespace v8 4340 } // namespace v8
4341 4341
4342 #endif // USE_SIMULATOR 4342 #endif // USE_SIMULATOR
4343 4343
4344 #endif // V8_TARGET_ARCH_MIPS 4344 #endif // V8_TARGET_ARCH_MIPS
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