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| 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.h - MIPS32 lowering ---*- C++-*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 /// | 9 /// |
| 10 /// \file | 10 /// \file |
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| 41 IceString getRegName(SizeT RegNum, Type Ty) const override; | 41 IceString getRegName(SizeT RegNum, Type Ty) const override; |
| 42 llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 42 llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
| 43 RegSetMask Exclude) const override; | 43 RegSetMask Exclude) const override; |
| 44 const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override { | 44 const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override { |
| 45 return TypeToRegisterSet[Ty]; | 45 return TypeToRegisterSet[Ty]; |
| 46 } | 46 } |
| 47 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { | 47 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { |
| 48 return RegisterAliases[Reg]; | 48 return RegisterAliases[Reg]; |
| 49 } | 49 } |
| 50 bool hasFramePointer() const override { return UsesFramePointer; } | 50 bool hasFramePointer() const override { return UsesFramePointer; } |
| 51 SizeT getStackReg() const override { return RegMIPS32::Reg_SP; } |
| 51 SizeT getFrameOrStackReg() const override { | 52 SizeT getFrameOrStackReg() const override { |
| 52 return UsesFramePointer ? RegMIPS32::Reg_FP : RegMIPS32::Reg_SP; | 53 return UsesFramePointer ? RegMIPS32::Reg_FP : RegMIPS32::Reg_SP; |
| 53 } | 54 } |
| 54 size_t typeWidthInBytesOnStack(Type Ty) const override { | 55 size_t typeWidthInBytesOnStack(Type Ty) const override { |
| 55 // Round up to the next multiple of 4 bytes. In particular, i1, i8, and i16 | 56 // Round up to the next multiple of 4 bytes. In particular, i1, i8, and i16 |
| 56 // are rounded up to 4 bytes. | 57 // are rounded up to 4 bytes. |
| 57 return (typeWidthInBytes(Ty) + 3) & ~3; | 58 return (typeWidthInBytes(Ty) + 3) & ~3; |
| 58 } | 59 } |
| 59 | 60 |
| 60 bool shouldSplitToVariable64On32(Type Ty) const override { | 61 bool shouldSplitToVariable64On32(Type Ty) const override { |
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| 180 protected: | 181 protected: |
| 181 explicit TargetHeaderMIPS32(GlobalContext *Ctx); | 182 explicit TargetHeaderMIPS32(GlobalContext *Ctx); |
| 182 | 183 |
| 183 private: | 184 private: |
| 184 ~TargetHeaderMIPS32() = default; | 185 ~TargetHeaderMIPS32() = default; |
| 185 }; | 186 }; |
| 186 | 187 |
| 187 } // end of namespace Ice | 188 } // end of namespace Ice |
| 188 | 189 |
| 189 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H | 190 #endif // SUBZERO_SRC_ICETARGETLOWERINGMIPS32_H |
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