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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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67 IceString getRegName(SizeT RegNum, Type Ty) const override; | 67 IceString getRegName(SizeT RegNum, Type Ty) const override; |
68 llvm::SmallBitVector getRegisterSet(RegSetMask Include, | 68 llvm::SmallBitVector getRegisterSet(RegSetMask Include, |
69 RegSetMask Exclude) const override; | 69 RegSetMask Exclude) const override; |
70 const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override { | 70 const llvm::SmallBitVector &getRegisterSetForType(Type Ty) const override { |
71 return TypeToRegisterSet[Ty]; | 71 return TypeToRegisterSet[Ty]; |
72 } | 72 } |
73 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { | 73 const llvm::SmallBitVector &getAliasesForRegister(SizeT Reg) const override { |
74 return RegisterAliases[Reg]; | 74 return RegisterAliases[Reg]; |
75 } | 75 } |
76 bool hasFramePointer() const override { return UsesFramePointer; } | 76 bool hasFramePointer() const override { return UsesFramePointer; } |
| 77 SizeT getStackReg() const override { return RegARM32::Reg_sp; } |
77 SizeT getFrameOrStackReg() const override { | 78 SizeT getFrameOrStackReg() const override { |
78 return UsesFramePointer ? RegARM32::Reg_fp : RegARM32::Reg_sp; | 79 return UsesFramePointer ? RegARM32::Reg_fp : RegARM32::Reg_sp; |
79 } | 80 } |
80 SizeT getReservedTmpReg() const { return RegARM32::Reg_ip; } | 81 SizeT getReservedTmpReg() const { return RegARM32::Reg_ip; } |
81 | 82 |
82 size_t typeWidthInBytesOnStack(Type Ty) const override { | 83 size_t typeWidthInBytesOnStack(Type Ty) const override { |
83 // Round up to the next multiple of 4 bytes. In particular, i1, i8, and i16 | 84 // Round up to the next multiple of 4 bytes. In particular, i1, i8, and i16 |
84 // are rounded up to 4 bytes. | 85 // are rounded up to 4 bytes. |
85 return (typeWidthInBytes(Ty) + 3) & ~3; | 86 return (typeWidthInBytes(Ty) + 3) & ~3; |
86 } | 87 } |
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582 | 583 |
583 private: | 584 private: |
584 ~TargetHeaderARM32() = default; | 585 ~TargetHeaderARM32() = default; |
585 | 586 |
586 TargetARM32Features CPUFeatures; | 587 TargetARM32Features CPUFeatures; |
587 }; | 588 }; |
588 | 589 |
589 } // end of namespace Ice | 590 } // end of namespace Ice |
590 | 591 |
591 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 592 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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