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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #include "vm/disassembler.h" | 5 #include "vm/disassembler.h" |
6 | 6 |
7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. | 7 #include "vm/globals.h" // Needed here to get TARGET_ARCH_ARM. |
8 #if defined(TARGET_ARCH_ARM) | 8 #if defined(TARGET_ARCH_ARM) |
9 #include "platform/assert.h" | 9 #include "platform/assert.h" |
10 | 10 |
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631 case 3: { | 631 case 3: { |
632 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. | 632 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. |
633 Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd"); | 633 Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd"); |
634 break; | 634 break; |
635 } | 635 } |
636 case 4: { | 636 case 4: { |
637 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. | 637 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. |
638 Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs"); | 638 Format(instr, "umull'cond's 'rd, 'rn, 'rm, 'rs"); |
639 break; | 639 break; |
640 } | 640 } |
| 641 case 6: { |
| 642 // Registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. |
| 643 Format(instr, "smull'cond's 'rd, 'rn, 'rm, 'rs"); |
| 644 break; |
| 645 } |
641 default: { | 646 default: { |
642 Unknown(instr); // Not used. | 647 Unknown(instr); // Not used. |
643 break; | 648 break; |
644 } | 649 } |
645 } | 650 } |
646 } else { | 651 } else { |
647 // synchronization primitives | 652 // synchronization primitives |
648 switch (instr->Bits(20, 4)) { | 653 switch (instr->Bits(20, 4)) { |
649 case 8: { | 654 case 8: { |
650 Format(instr, "strex'cond 'rd, 'rm, ['rn]"); | 655 Format(instr, "strex'cond 'rd, 'rm, ['rn]"); |
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1301 human_buffer, | 1306 human_buffer, |
1302 sizeof(human_buffer), | 1307 sizeof(human_buffer), |
1303 pc); | 1308 pc); |
1304 pc += instruction_length; | 1309 pc += instruction_length; |
1305 } | 1310 } |
1306 } | 1311 } |
1307 | 1312 |
1308 } // namespace dart | 1313 } // namespace dart |
1309 | 1314 |
1310 #endif // defined TARGET_ARCH_ARM | 1315 #endif // defined TARGET_ARCH_ARM |
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