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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 | 4 |
5 #include "vm/globals.h" | 5 #include "vm/globals.h" |
6 #if defined(TARGET_ARCH_ARM) | 6 #if defined(TARGET_ARCH_ARM) |
7 | 7 |
8 #include "vm/assembler.h" | 8 #include "vm/assembler.h" |
9 #include "vm/simulator.h" | 9 #include "vm/simulator.h" |
10 #include "vm/runtime_entry.h" | 10 #include "vm/runtime_entry.h" |
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458 } | 458 } |
459 | 459 |
460 | 460 |
461 void Assembler::mls(Register rd, Register rn, | 461 void Assembler::mls(Register rd, Register rn, |
462 Register rm, Register ra, Condition cond) { | 462 Register rm, Register ra, Condition cond) { |
463 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. | 463 // Assembler registers rd, rn, rm, ra are encoded as rn, rm, rs, rd. |
464 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm); | 464 EmitMulOp(cond, B22 | B21, ra, rd, rn, rm); |
465 } | 465 } |
466 | 466 |
467 | 467 |
| 468 void Assembler::smull(Register rd_lo, Register rd_hi, |
| 469 Register rn, Register rm, Condition cond) { |
| 470 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. |
| 471 EmitMulOp(cond, B23 | B22, rd_lo, rd_hi, rn, rm); |
| 472 } |
| 473 |
| 474 |
468 void Assembler::umull(Register rd_lo, Register rd_hi, | 475 void Assembler::umull(Register rd_lo, Register rd_hi, |
469 Register rn, Register rm, Condition cond) { | 476 Register rn, Register rm, Condition cond) { |
470 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. | 477 // Assembler registers rd_lo, rd_hi, rn, rm are encoded as rd, rn, rm, rs. |
471 EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm); | 478 EmitMulOp(cond, B23, rd_lo, rd_hi, rn, rm); |
472 } | 479 } |
473 | 480 |
474 | 481 |
475 void Assembler::EmitDivOp(Condition cond, int32_t opcode, | 482 void Assembler::EmitDivOp(Condition cond, int32_t opcode, |
476 Register rd, Register rn, Register rm) { | 483 Register rd, Register rn, Register rm) { |
477 ASSERT(CPUFeatures::integer_division_supported()); | 484 ASSERT(CPUFeatures::integer_division_supported()); |
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2116 | 2123 |
2117 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 2124 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
2118 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 2125 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
2119 return fpu_reg_names[reg]; | 2126 return fpu_reg_names[reg]; |
2120 } | 2127 } |
2121 | 2128 |
2122 } // namespace dart | 2129 } // namespace dart |
2123 | 2130 |
2124 #endif // defined TARGET_ARCH_ARM | 2131 #endif // defined TARGET_ARCH_ARM |
2125 | 2132 |
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