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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
2 // for details. All rights reserved. Use of this source code is governed by a | 2 // for details. All rights reserved. Use of this source code is governed by a |
3 // BSD-style license that can be found in the LICENSE file. | 3 // BSD-style license that can be found in the LICENSE file. |
4 // | 4 // |
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe | 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe |
6 // Please update the (git) revision if we merge changes from Dart. | 6 // Please update the (git) revision if we merge changes from Dart. |
7 // https://code.google.com/p/dart/wiki/GettingTheSource | 7 // https://code.google.com/p/dart/wiki/GettingTheSource |
8 | 8 |
9 #include "vm/globals.h" // NOLINT | 9 #include "vm/globals.h" // NOLINT |
10 #if defined(TARGET_ARCH_ARM) | 10 #if defined(TARGET_ARCH_ARM) |
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1426 QRegister qd, QRegister qn, QRegister qm) { | 1426 QRegister qd, QRegister qn, QRegister qm) { |
1427 EmitSIMDqqq(B24 | B9 | B8, sz, qd, qn, qm); | 1427 EmitSIMDqqq(B24 | B9 | B8, sz, qd, qn, qm); |
1428 } | 1428 } |
1429 | 1429 |
1430 | 1430 |
1431 void Assembler::vcgtqs(QRegister qd, QRegister qn, QRegister qm) { | 1431 void Assembler::vcgtqs(QRegister qd, QRegister qn, QRegister qm) { |
1432 EmitSIMDqqq(B24 | B21 | B11 | B10 | B9, kSWord, qd, qn, qm); | 1432 EmitSIMDqqq(B24 | B21 | B11 | B10 | B9, kSWord, qd, qn, qm); |
1433 } | 1433 } |
1434 | 1434 |
1435 | 1435 |
| 1436 #if 0 |
| 1437 // Moved to: ARM32::AssemblerARM32. |
1436 void Assembler::bkpt(uint16_t imm16) { | 1438 void Assembler::bkpt(uint16_t imm16) { |
1437 Emit(BkptEncoding(imm16)); | 1439 Emit(BkptEncoding(imm16)); |
1438 } | 1440 } |
| 1441 #endif |
1439 | 1442 |
1440 | 1443 |
1441 void Assembler::b(Label* label, Condition cond) { | 1444 void Assembler::b(Label* label, Condition cond) { |
1442 EmitBranch(cond, label, false); | 1445 EmitBranch(cond, label, false); |
1443 } | 1446 } |
1444 | 1447 |
1445 | 1448 |
1446 void Assembler::bl(Label* label, Condition cond) { | 1449 void Assembler::bl(Label* label, Condition cond) { |
1447 EmitBranch(cond, label, true); | 1450 EmitBranch(cond, label, true); |
1448 } | 1451 } |
1449 | 1452 |
1450 | 1453 #if 0 |
| 1454 // Moved to: ARM32::AssemblerARM32. |
1451 void Assembler::bx(Register rm, Condition cond) { | 1455 void Assembler::bx(Register rm, Condition cond) { |
1452 ASSERT(rm != kNoRegister); | 1456 ASSERT(rm != kNoRegister); |
1453 ASSERT(cond != kNoCondition); | 1457 ASSERT(cond != kNoCondition); |
1454 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 1458 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
1455 B24 | B21 | (0xfff << 8) | B4 | | 1459 B24 | B21 | (0xfff << 8) | B4 | |
1456 (static_cast<int32_t>(rm) << kRmShift); | 1460 (static_cast<int32_t>(rm) << kRmShift); |
1457 Emit(encoding); | 1461 Emit(encoding); |
1458 } | 1462 } |
| 1463 #endif |
1459 | 1464 |
1460 | 1465 |
1461 void Assembler::blx(Register rm, Condition cond) { | 1466 void Assembler::blx(Register rm, Condition cond) { |
1462 ASSERT(rm != kNoRegister); | 1467 ASSERT(rm != kNoRegister); |
1463 ASSERT(cond != kNoCondition); | 1468 ASSERT(cond != kNoCondition); |
1464 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | | 1469 int32_t encoding = (static_cast<int32_t>(cond) << kConditionShift) | |
1465 B24 | B21 | (0xfff << 8) | B5 | B4 | | 1470 B24 | B21 | (0xfff << 8) | B5 | B4 | |
1466 (static_cast<int32_t>(rm) << kRmShift); | 1471 (static_cast<int32_t>(rm) << kRmShift); |
1467 Emit(encoding); | 1472 Emit(encoding); |
1468 } | 1473 } |
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2307 } else { | 2312 } else { |
2308 int32_t next = buffer_.Load<int32_t>(position); | 2313 int32_t next = buffer_.Load<int32_t>(position); |
2309 int32_t encoded = Assembler::EncodeBranchOffset(dest, next); | 2314 int32_t encoded = Assembler::EncodeBranchOffset(dest, next); |
2310 buffer_.Store<int32_t>(position, encoded); | 2315 buffer_.Store<int32_t>(position, encoded); |
2311 label->position_ = Assembler::DecodeBranchOffset(next); | 2316 label->position_ = Assembler::DecodeBranchOffset(next); |
2312 } | 2317 } |
2313 } | 2318 } |
2314 label->BindTo(bound_pc); | 2319 label->BindTo(bound_pc); |
2315 } | 2320 } |
2316 | 2321 |
2317 | 2322 #if 0 |
| 2323 // Moved to: ARM32::AssemblerARM32 as method bind(Label* Label) |
| 2324 // Note: Most of this code isn't needed because instruction selection has |
| 2325 // already been handler |
2318 void Assembler::BindARMv7(Label* label) { | 2326 void Assembler::BindARMv7(Label* label) { |
2319 ASSERT(!label->IsBound()); | 2327 ASSERT(!label->IsBound()); |
2320 intptr_t bound_pc = buffer_.Size(); | 2328 intptr_t bound_pc = buffer_.Size(); |
2321 while (label->IsLinked()) { | 2329 while (label->IsLinked()) { |
2322 const int32_t position = label->Position(); | 2330 const int32_t position = label->Position(); |
2323 int32_t dest = bound_pc - position; | 2331 int32_t dest = bound_pc - position; |
2324 if (use_far_branches() && !CanEncodeBranchOffset(dest)) { | 2332 if (use_far_branches() && !CanEncodeBranchOffset(dest)) { |
2325 // Far branches are enabled and we can't encode the branch offset. | 2333 // Far branches are enabled and we can't encode the branch offset. |
2326 | 2334 |
2327 // Grab instructions that load the offset. | 2335 // Grab instructions that load the offset. |
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2374 label->position_ = DecodeARMv7LoadImmediate(movt, movw); | 2382 label->position_ = DecodeARMv7LoadImmediate(movt, movw); |
2375 } else { | 2383 } else { |
2376 int32_t next = buffer_.Load<int32_t>(position); | 2384 int32_t next = buffer_.Load<int32_t>(position); |
2377 int32_t encoded = Assembler::EncodeBranchOffset(dest, next); | 2385 int32_t encoded = Assembler::EncodeBranchOffset(dest, next); |
2378 buffer_.Store<int32_t>(position, encoded); | 2386 buffer_.Store<int32_t>(position, encoded); |
2379 label->position_ = Assembler::DecodeBranchOffset(next); | 2387 label->position_ = Assembler::DecodeBranchOffset(next); |
2380 } | 2388 } |
2381 } | 2389 } |
2382 label->BindTo(bound_pc); | 2390 label->BindTo(bound_pc); |
2383 } | 2391 } |
| 2392 #endif |
2384 | 2393 |
2385 | 2394 |
2386 void Assembler::Bind(Label* label) { | 2395 void Assembler::Bind(Label* label) { |
2387 const ARMVersion version = TargetCPUFeatures::arm_version(); | 2396 const ARMVersion version = TargetCPUFeatures::arm_version(); |
2388 if ((version == ARMv5TE) || (version == ARMv6)) { | 2397 if ((version == ARMv5TE) || (version == ARMv6)) { |
2389 BindARMv6(label); | 2398 BindARMv6(label); |
2390 } else { | 2399 } else { |
2391 ASSERT(version == ARMv7); | 2400 ASSERT(version == ARMv7); |
2392 BindARMv7(label); | 2401 BindARMv7(label); |
2393 } | 2402 } |
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3644 | 3653 |
3645 | 3654 |
3646 const char* Assembler::FpuRegisterName(FpuRegister reg) { | 3655 const char* Assembler::FpuRegisterName(FpuRegister reg) { |
3647 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); | 3656 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); |
3648 return fpu_reg_names[reg]; | 3657 return fpu_reg_names[reg]; |
3649 } | 3658 } |
3650 | 3659 |
3651 } // namespace dart | 3660 } // namespace dart |
3652 | 3661 |
3653 #endif // defined TARGET_ARCH_ARM | 3662 #endif // defined TARGET_ARCH_ARM |
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