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Side by Side Diff: src/DartARM32/assembler_arm.cc

Issue 1397043003: Fix emission of move immediate for ARM integrated assembler. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Clean up header file for IceAssemblerARM. Created 5 years, 2 months ago
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1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file 1 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file
2 // for details. All rights reserved. Use of this source code is governed by a 2 // for details. All rights reserved. Use of this source code is governed by a
3 // BSD-style license that can be found in the LICENSE file. 3 // BSD-style license that can be found in the LICENSE file.
4 // 4 //
5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe 5 // This is forked from Dart revision df52deea9f25690eb8b66c5995da92b70f7ac1fe
6 // Please update the (git) revision if we merge changes from Dart. 6 // Please update the (git) revision if we merge changes from Dart.
7 // https://code.google.com/p/dart/wiki/GettingTheSource 7 // https://code.google.com/p/dart/wiki/GettingTheSource
8 8
9 #include "vm/globals.h" // NOLINT 9 #include "vm/globals.h" // NOLINT
10 #if defined(TARGET_ARCH_ARM) 10 #if defined(TARGET_ARCH_ARM)
(...skipping 53 matching lines...) Expand 10 before | Expand all | Expand 10 after
64 data += 4; 64 data += 4;
65 } 65 }
66 } 66 }
67 67
68 68
69 void Assembler::Emit(int32_t value) { 69 void Assembler::Emit(int32_t value) {
70 AssemblerBuffer::EnsureCapacity ensured(&buffer_); 70 AssemblerBuffer::EnsureCapacity ensured(&buffer_);
71 buffer_.Emit<int32_t>(value); 71 buffer_.Emit<int32_t>(value);
72 } 72 }
73 73
74 74 #if 0
75 // Moved to class AssemblerARM32.
75 void Assembler::EmitType01(Condition cond, 76 void Assembler::EmitType01(Condition cond,
76 int type, 77 int type,
77 Opcode opcode, 78 Opcode opcode,
78 int set_cc, 79 int set_cc,
79 Register rn, 80 Register rn,
80 Register rd, 81 Register rd,
81 Operand o) { 82 Operand o) {
82 ASSERT(rd != kNoRegister); 83 ASSERT(rd != kNoRegister);
83 ASSERT(cond != kNoCondition); 84 ASSERT(cond != kNoCondition);
84 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 85 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
85 type << kTypeShift | 86 type << kTypeShift |
86 static_cast<int32_t>(opcode) << kOpcodeShift | 87 static_cast<int32_t>(opcode) << kOpcodeShift |
87 set_cc << kSShift | 88 set_cc << kSShift |
88 static_cast<int32_t>(rn) << kRnShift | 89 static_cast<int32_t>(rn) << kRnShift |
89 static_cast<int32_t>(rd) << kRdShift | 90 static_cast<int32_t>(rd) << kRdShift |
90 o.encoding(); 91 o.encoding();
91 Emit(encoding); 92 Emit(encoding);
92 } 93 }
93 94 #endif
94 95
95 void Assembler::EmitType5(Condition cond, int32_t offset, bool link) { 96 void Assembler::EmitType5(Condition cond, int32_t offset, bool link) {
96 ASSERT(cond != kNoCondition); 97 ASSERT(cond != kNoCondition);
97 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift | 98 int32_t encoding = static_cast<int32_t>(cond) << kConditionShift |
98 5 << kTypeShift | 99 5 << kTypeShift |
99 (link ? 1 : 0) << kLinkShift; 100 (link ? 1 : 0) << kLinkShift;
100 Emit(Assembler::EncodeBranchOffset(offset, encoding)); 101 Emit(Assembler::EncodeBranchOffset(offset, encoding));
101 } 102 }
102 103
103 104
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270 void Assembler::orr(Register rd, Register rn, Operand o, Condition cond) { 271 void Assembler::orr(Register rd, Register rn, Operand o, Condition cond) {
271 EmitType01(cond, o.type(), ORR, 0, rn, rd, o); 272 EmitType01(cond, o.type(), ORR, 0, rn, rd, o);
272 } 273 }
273 274
274 275
275 void Assembler::orrs(Register rd, Register rn, Operand o, Condition cond) { 276 void Assembler::orrs(Register rd, Register rn, Operand o, Condition cond) {
276 EmitType01(cond, o.type(), ORR, 1, rn, rd, o); 277 EmitType01(cond, o.type(), ORR, 1, rn, rd, o);
277 } 278 }
278 279
279 280
281 #if 0
282 // Moved to AssemblerARM32::mov(..FlexImm..)
283 // TODO(kschimpf) other forms of move.
280 void Assembler::mov(Register rd, Operand o, Condition cond) { 284 void Assembler::mov(Register rd, Operand o, Condition cond) {
281 EmitType01(cond, o.type(), MOV, 0, R0, rd, o); 285 EmitType01(cond, o.type(), MOV, 0, R0, rd, o);
282 } 286 }
283 287 #endif
284 288
285 void Assembler::movs(Register rd, Operand o, Condition cond) { 289 void Assembler::movs(Register rd, Operand o, Condition cond) {
286 EmitType01(cond, o.type(), MOV, 1, R0, rd, o); 290 EmitType01(cond, o.type(), MOV, 1, R0, rd, o);
287 } 291 }
288 292
289 293
290 void Assembler::bic(Register rd, Register rn, Operand o, Condition cond) { 294 void Assembler::bic(Register rd, Register rn, Operand o, Condition cond) {
291 EmitType01(cond, o.type(), BIC, 0, rn, rd, o); 295 EmitType01(cond, o.type(), BIC, 0, rn, rd, o);
292 } 296 }
293 297
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3653 3657
3654 3658
3655 const char* Assembler::FpuRegisterName(FpuRegister reg) { 3659 const char* Assembler::FpuRegisterName(FpuRegister reg) {
3656 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters)); 3660 ASSERT((0 <= reg) && (reg < kNumberOfFpuRegisters));
3657 return fpu_reg_names[reg]; 3661 return fpu_reg_names[reg];
3658 } 3662 }
3659 3663
3660 } // namespace dart 3664 } // namespace dart
3661 3665
3662 #endif // defined TARGET_ARCH_ARM 3666 #endif // defined TARGET_ARCH_ARM
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