tests_lit/llvm2ice_tests/64bit.pnacl.ll - Issue 1396923002: Subzero: Remove trailing whitespace.

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Side by Side Diff: tests_lit/llvm2ice_tests/64bit.pnacl.ll

Issue 1396923002: Subzero: Remove trailing whitespace. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master

Patch Set: Created 5 years, 2 months ago

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1 ; This tries to be a comprehensive test of i64 operations, in	1 ; This tries to be a comprehensive test of i64 operations, in

2 ; particular the patterns for lowering i64 operations into constituent	2 ; particular the patterns for lowering i64 operations into constituent

3 ; i32 operations on x86-32.	3 ; i32 operations on x86-32.

4	4

5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \	5 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \

6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \	6 ; RUN: --target x8632 -i %s --args -O2 -allow-externally-defined-symbols \

7 ; RUN: \| %if --need=target_X8632 --command FileCheck %s	7 ; RUN: \| %if --need=target_X8632 --command FileCheck %s

8	8

9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \	9 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \

10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \	10 ; RUN: --target x8632 -i %s --args -Om1 -allow-externally-defined-symbols \

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510 ; OPTM1: test {{.*}},0x20	510 ; OPTM1: test {{.*}},0x20

511 ; OPTM1: je	511 ; OPTM1: je

512 ; OPTM1: sar {{.*}},0x1f	512 ; OPTM1: sar {{.*}},0x1f

513	513

514 ; ARM32-LABEL: shr64BitSigned	514 ; ARM32-LABEL: shr64BitSigned

515 ; ARM32: lsr [[T0:r[0-9]+]], r0, r2	515 ; ARM32: lsr [[T0:r[0-9]+]], r0, r2

516 ; ARM32: rsb [[T1:r[0-9]+]], r2, #32	516 ; ARM32: rsb [[T1:r[0-9]+]], r2, #32

517 ; ARM32: orr r0, [[T0]], r1, lsl [[T1]]	517 ; ARM32: orr r0, [[T0]], r1, lsl [[T1]]

518 ; ARM32: sub [[T2:r[0-9]+]], r2, #32	518 ; ARM32: sub [[T2:r[0-9]+]], r2, #32

519 ; ARM32: cmp [[T2]], #0	519 ; ARM32: cmp [[T2]], #0

520 ; ARM32: asrge r0, r1, [[T2]]	520 ; ARM32: asrge r0, r1, [[T2]]

521 ; ARM32: asr r{{[0-9]+}}, r1, r2	521 ; ARM32: asr r{{[0-9]+}}, r1, r2

522	522

523 define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {	523 define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {

524 entry:	524 entry:

525 %shr = ashr i64 %a, %b	525 %shr = ashr i64 %a, %b

526 %result = trunc i64 %shr to i32	526 %result = trunc i64 %shr to i32

527 ret i32 %result	527 ret i32 %result

528 }	528 }

529 ; CHECK-LABEL: shr64BitSignedTrunc	529 ; CHECK-LABEL: shr64BitSignedTrunc

530 ; CHECK: shrd	530 ; CHECK: shrd

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1810 ; CHECK-LABEL: phi64Undef	1810 ; CHECK-LABEL: phi64Undef

1811 ; CHECK: mov {{.*}},0x0	1811 ; CHECK: mov {{.*}},0x0

1812 ; CHECK: mov {{.*}},0x0	1812 ; CHECK: mov {{.*}},0x0

1813 ; OPTM1-LABEL: phi64Undef	1813 ; OPTM1-LABEL: phi64Undef

1814 ; OPTM1: mov {{.*}},0x0	1814 ; OPTM1: mov {{.*}},0x0

1815 ; OPTM1: mov {{.*}},0x0	1815 ; OPTM1: mov {{.*}},0x0

1816 ; ARM32-LABEL: phi64Undef	1816 ; ARM32-LABEL: phi64Undef

1817 ; ARM32: mov {{.*}} #0	1817 ; ARM32: mov {{.*}} #0

1818 ; ARM32: mov {{.*}} #0	1818 ; ARM32: mov {{.*}} #0

1819	1819

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