Subzero: Remove trailing whitespace.

src/IceInstARM32.def

 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines properties of ARM32 instructions in the form of x-macros.
@@ skipping 96 matching lines @@
 
 // S registers 0-15 are scratch, but 16-31 are preserved.
 // Regenerate this with the following python script:
 //
 // def print_sregs():
 //   for i in xrange(0, 32):
 //     is_scratch = 1 if i < 16 else 0
 //     is_preserved = 1 if i >= 16 else 0
 //     print ('  X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' +
 //            '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, 0, ' +
-//            'ALIASES(Reg_s{regnum_s:<2}, Reg_d{regnum:<2}, ' + 
+//            'ALIASES(Reg_s{regnum_s:<2}, Reg_d{regnum:<2}, ' +
 //            'Reg_q{regnum_q:<2}))    \\').format(
 //            regnum=i, regnum_d=i>>1,
 //            regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved)
 //
 // print_sregs()
 //
 #define REGARM32_FP32_TABLE                                                    \
   /* val, encode, name, scratch, preserved, stackptr, frameptr,                \
      isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init */               \
   X(Reg_s0 , 0 , "s0" , 1, 0, 0, 0, 0, 0, 1, 0, 0,                             \
@@ skipping 52 matching lines @@
     ALIASES3(Reg_s26, Reg_d13, Reg_q6))                                        \
   X(Reg_s27, 27, "s27", 0, 1, 0, 0, 0, 0, 1, 0, 0,                             \
     ALIASES3(Reg_s27, Reg_d13, Reg_q6))                                        \
   X(Reg_s28, 28, "s28", 0, 1, 0, 0, 0, 0, 1, 0, 0,                             \
     ALIASES3(Reg_s28, Reg_d14, Reg_q7))                                        \
   X(Reg_s29, 29, "s29", 0, 1, 0, 0, 0, 0, 1, 0, 0,                             \
     ALIASES3(Reg_s29, Reg_d14, Reg_q7))                                        \
   X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 0, 1, 0, 0,                             \
     ALIASES3(Reg_s30, Reg_d15, Reg_q7))                                        \
   X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 0, 1, 0, 0,                             \
-    ALIASES3(Reg_s31, Reg_d15, Reg_q7)) 
+    ALIASES3(Reg_s31, Reg_d15, Reg_q7))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32,isFP64, isVec128, aliases_init)
 
 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch
 // (if supported by the D32 feature vs D16). D registers are defined in reverse
 // order so that, during register allocation, Subzero will prefer higher D
 // registers. In processors supporting the D32 feature this will effectively
 // cause double allocation to bias towards allocating "high" D registers, which
 // do not alias any S registers.
 //
@@ skipping 78 matching lines @@
     ALIASES4(Reg_s10, Reg_s11, Reg_d5 , Reg_q2))                               \
   X(Reg_d4 , 4 ,  "d4", 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
     ALIASES4(Reg_s8 , Reg_s9 , Reg_d4 , Reg_q2))                               \
   X(Reg_d3 , 3 ,  "d3", 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
     ALIASES4(Reg_s6 , Reg_s7 , Reg_d3 , Reg_q1))                               \
   X(Reg_d2 , 2 ,  "d2", 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
     ALIASES4(Reg_s4 , Reg_s5 , Reg_d2 , Reg_q1))                               \
   X(Reg_d1 , 1 ,  "d1", 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
     ALIASES4(Reg_s2 , Reg_s3 , Reg_d1 , Reg_q0))                               \
   X(Reg_d0 , 0 ,  "d0", 1, 0, 0, 0, 0, 0, 0, 1, 0,                             \
-    ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0)) 
+    ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init)
 
 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch
 // (if supported by the D32 feature). Q registers are defined in reverse order
 // for the same reason as D registers.
 //
 // Regenerate this with the following python script:
 // def print_qregs():
 //   for i in xrange(15, 7, -1):
@@ skipping 47 matching lines @@
     ALIASES7(Reg_s20, Reg_s21, Reg_s22, Reg_s23, Reg_d10, Reg_d11, Reg_q5))    \
   X(Reg_q4 , 4 , "q4", 0, 1, 0, 0, 0, 0, 0, 0, 1,                              \
     ALIASES7(Reg_s16, Reg_s17, Reg_s18, Reg_s19, Reg_d8 , Reg_d9 , Reg_q4))    \
   X(Reg_q3 , 3 , "q3", 1, 0, 0, 0, 0, 0, 0, 0, 1,                              \
     ALIASES7(Reg_s12, Reg_s13, Reg_s14, Reg_s15, Reg_d6 , Reg_d7 , Reg_q3))    \
   X(Reg_q2 , 2 , "q2", 1, 0, 0, 0, 0, 0, 0, 0, 1,                              \
     ALIASES7(Reg_s8 , Reg_s9 , Reg_s10, Reg_s11, Reg_d4 , Reg_d5 , Reg_q2))    \
   X(Reg_q1 , 1 , "q1", 1, 0, 0, 0, 0, 0, 0, 0, 1,                              \
     ALIASES7(Reg_s4 , Reg_s5 , Reg_s6 , Reg_s7 , Reg_d2 , Reg_d3 , Reg_q1))    \
   X(Reg_q0 , 0 , "q0", 1, 0, 0, 0, 0, 0, 0, 0, 1,                              \
-    ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0)) 
+    ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0))
 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
 //          isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
 #undef ALIASES
 
 // We also provide a combined table, so that there is a namespace where all of
 // the registers are considered and have distinct numberings. This is in
 // contrast to the above, where the "encode" is based on how the register
 // numbers will be encoded in binaries and values can overlap.
 #define REGARM32_TABLE                                                         \
   /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt,         \
@@ skipping 70 matching lines @@
   X(LS, 9 , HI, "ls")   /* unsigned lower or same */                           \
   X(GE, 10, LT, "ge")  /* signed greater than or equal */                      \
   X(LT, 11, GE, "lt")  /* signed less than */                                  \
   X(GT, 12, LE, "gt")  /* signed greater than */                               \
   X(LE, 13, GT, "le")  /* signed less than or equal */                         \
   X(AL, 14, kNone, "") /* always (unconditional) */                            \
   X(kNone, 15, kNone, "??") /* special condition / none */
 //#define X(tag, encode, opp, emit)
 
 #endif // SUBZERO_SRC_ICEINSTARM32_DEF