MIPS: r6 compact branch optimization.

src/mips/assembler-mips-inl.h

 
 // Copyright (c) 1994-2006 Sun Microsystems Inc.
 // All Rights Reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 // - Redistributions of source code must retain the above copyright notice,
 // this list of conditions and the following disclaimer.
@@ skipping 431 matching lines @@
   if (pc_offset() >= next_buffer_check_ - extra_instructions * kInstrSize) {
     CheckTrampolinePool();
   }
 }
 
 
 void Assembler::emit(Instr x) {
   if (!is_buffer_growth_blocked()) {
     CheckBuffer();
   }
+  if (IsPrevInstrCompactBranch()) {
+    BlockTrampolinePoolFor(1);  // For saving forbidden slot.

[paul.l..., 2015/10/15 01:51:24]

Doesn't this BlockTrampolinePoolFor(1) come too late to work here? 

You just did a CheckBuffer() above, which could emit a trampoline. I think you
need to move this block above that one.

[balazs.kilvady, 2015/10/30 21:11:14]

Done.

+    if (Instruction::At(reinterpret_cast<byte*>(&x))
+            ->IsForbiddenInBranchDelay()) {

[paul.l..., 2015/10/15 01:51:24]

I think the use of 'Delay' in this name is mis-leading. We have two similar
concepts, regular (old-style) branches do have Branch Delay slots, and they are
present in all revs including r6. Compact Branches do not have delay slots, they
have forbidden slots. This still is all plenty confusing already, and I think we
must be extra-careful with our naming and comments, to help keep this as clear
as possible.

In this case, you are _only_ in this block after a compact branch, and so by
definition, you do NOT have a delay slot.

Suggest you call this IsForbiddenAfterBranch() or
IsForbiddenAfterCompactBranch()

[balazs.kilvady, 2015/10/30 21:11:14]

Done.

+      // Nop instruction to preceed a CTI in forbidden slot:
+      Instr nop = SPECIAL | SLL;
+      *reinterpret_cast<Instr*>(pc_) = nop;
+      pc_ += kInstrSize;
+    }
+    ClearCompactBranchState();
+  }
   *reinterpret_cast<Instr*>(pc_) = x;
   pc_ += kInstrSize;
   CheckTrampolinePoolQuick();
 }
 
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_MIPS_ASSEMBLER_MIPS_INL_H_