Subzero: Don't "and" i1 values with 1.

tests_lit/llvm2ice_tests/test_i1.ll

 ; Tests various aspects of i1 related lowering.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
@@ skipping 69 matching lines @@
 entry:
   %arg_i1 = trunc i32 %arg to i1
   %result_i8 = zext i1 %arg_i1 to i8
   %result = zext i8 %result_i8 to i32
   ret i32 %result
 }
 ; CHECK-LABEL: testZextI8
 ; match the trunc instruction
 ; CHECK: and {{.*}},0x1
 ; match the zext i1 instruction (NOTE: no mov need between i1 and i8).
-; CHECK: and {{.*}},0x1
+; CHECK-NOT: and {{.*}},0x1
 ; ARM32-LABEL: testZextI8
 ; ARM32: and {{.*}}, #1
 ; ARM32: and {{.*}}, #1
 
 ; Test zext to i16.
 define internal i32 @testZextI16(i32 %arg) {
 entry:
   %arg_i1 = trunc i32 %arg to i1
   %result_i16 = zext i1 %arg_i1 to i16
   %result = zext i16 %result_i16 to i32
   ret i32 %result
 }
 ; CHECK-LABEL: testZextI16
 ; match the trunc instruction
 ; CHECK: and {{.*}},0x1
 ; match the zext i1 instruction (note 32-bit reg is used because it's shorter).
 ; CHECK: movzx [[REG:e.*]],{{[a-d]l|BYTE PTR}}
-; CHECK: and [[REG]],0x1
+; CHECK-NOT: and [[REG]],0x1
 
 ; ARM32-LABEL: testZextI16
 ; match the trunc instruction
 ; ARM32: and {{.*}}, #1
 ; match the zext (no need to uxt into a reg if src is already in a reg)
 ; ARM32: and {{.*}}, #1
 
 ; Test zext to i32.
 define internal i32 @testZextI32(i32 %arg) {
 entry:
   %arg_i1 = trunc i32 %arg to i1
   %result_i32 = zext i1 %arg_i1 to i32
   ret i32 %result_i32
 }
 ; CHECK-LABEL: testZextI32
 ; match the trunc instruction
 ; CHECK: and {{.*}},0x1
 ; match the zext i1 instruction
 ; CHECK: movzx
-; CHECK: and {{.*}},0x1
+; CHECK-NOT: and {{.*}},0x1
 ; ARM32-LABEL: testZextI32
 ; ARM32: and {{.*}}, #1
 ; ARM32: and {{.*}}, #1
 
 ; Test zext to i64.
 define internal i64 @testZextI64(i32 %arg) {
 entry:
   %arg_i1 = trunc i32 %arg to i1
   %result_i64 = zext i1 %arg_i1 to i64
   ret i64 %result_i64
 }
 ; CHECK-LABEL: testZextI64
 ; match the trunc instruction
 ; CHECK: and {{.*}},0x1
 ; match the zext i1 instruction
 ; CHECK: movzx
-; CHECK: and {{.*}},0x1
 ; CHECK: mov {{.*}},0x0
 ; ARM32-LABEL: testZextI64
 ; ARM32: and {{.*}}, #1
 ; ARM32: and {{.*}}, #1
 ; ARM32: mov {{.*}}, #0
 
 ; Test sext to i8.
 define internal i32 @testSextI8(i32 %arg) {
 entry:
   %arg_i1 = trunc i32 %arg to i1
@@ skipping 94 matching lines @@
 ; ARM32: mov{{.*}}, #1
 ; ARM32: lsl
 ; ARM32: asr
 
 define internal i32 @testZextTrue() {
   %result = zext i1 true to i32
   ret i32 %result
 }
 ; CHECK-LABEL: testZextTrue
 ; CHECK: movzx
-; CHECK: and {{.*}},0x1
+; CHECK-NOT: and {{.*}},0x1
 ; ARM32-LABEL: testZextTrue
 ; ARM32: mov{{.*}}, #1
 ; ARM32: and {{.*}}, #1
 
 ; Test fptosi float to i1.
 define internal i32 @testFptosiFloat(float %arg) {
 entry:
   %arg_i1 = fptosi float %arg to i1
   %result = sext i1 %arg_i1 to i32
   ret i32 %result
@@ skipping 11 matching lines @@
   %arg_i1 = fptosi double %arg to i1
   %result = sext i1 %arg_i1 to i32
   ret i32 %result
 }
 ; CHECK-LABEL: testFptosiDouble
 ; CHECK: cvttsd2si
 ; CHECK: and {{.*}},0x1
 ; CHECK: movzx [[REG:.*]],
 ; CHECK-NEXT: shl [[REG]],0x1f
 ; CHECK-NEXT: sar [[REG]],0x1f