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1 ; Tests various aspects of i1 related lowering. | 1 ; Tests various aspects of i1 related lowering. |
2 | 2 |
3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ | 3 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ |
4 ; RUN: --target x8632 -i %s --args -O2 \ | 4 ; RUN: --target x8632 -i %s --args -O2 \ |
5 ; RUN: | %if --need=target_X8632 --command FileCheck %s | 5 ; RUN: | %if --need=target_X8632 --command FileCheck %s |
6 | 6 |
7 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ | 7 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \ |
8 ; RUN: --target x8632 -i %s --args -Om1 \ | 8 ; RUN: --target x8632 -i %s --args -Om1 \ |
9 ; RUN: | %if --need=target_X8632 --command FileCheck %s | 9 ; RUN: | %if --need=target_X8632 --command FileCheck %s |
10 | 10 |
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80 entry: | 80 entry: |
81 %arg_i1 = trunc i32 %arg to i1 | 81 %arg_i1 = trunc i32 %arg to i1 |
82 %result_i8 = zext i1 %arg_i1 to i8 | 82 %result_i8 = zext i1 %arg_i1 to i8 |
83 %result = zext i8 %result_i8 to i32 | 83 %result = zext i8 %result_i8 to i32 |
84 ret i32 %result | 84 ret i32 %result |
85 } | 85 } |
86 ; CHECK-LABEL: testZextI8 | 86 ; CHECK-LABEL: testZextI8 |
87 ; match the trunc instruction | 87 ; match the trunc instruction |
88 ; CHECK: and {{.*}},0x1 | 88 ; CHECK: and {{.*}},0x1 |
89 ; match the zext i1 instruction (NOTE: no mov need between i1 and i8). | 89 ; match the zext i1 instruction (NOTE: no mov need between i1 and i8). |
90 ; CHECK: and {{.*}},0x1 | 90 ; CHECK-NOT: and {{.*}},0x1 |
91 ; ARM32-LABEL: testZextI8 | 91 ; ARM32-LABEL: testZextI8 |
92 ; ARM32: and {{.*}}, #1 | 92 ; ARM32: and {{.*}}, #1 |
93 ; ARM32: and {{.*}}, #1 | 93 ; ARM32: and {{.*}}, #1 |
94 | 94 |
95 ; Test zext to i16. | 95 ; Test zext to i16. |
96 define internal i32 @testZextI16(i32 %arg) { | 96 define internal i32 @testZextI16(i32 %arg) { |
97 entry: | 97 entry: |
98 %arg_i1 = trunc i32 %arg to i1 | 98 %arg_i1 = trunc i32 %arg to i1 |
99 %result_i16 = zext i1 %arg_i1 to i16 | 99 %result_i16 = zext i1 %arg_i1 to i16 |
100 %result = zext i16 %result_i16 to i32 | 100 %result = zext i16 %result_i16 to i32 |
101 ret i32 %result | 101 ret i32 %result |
102 } | 102 } |
103 ; CHECK-LABEL: testZextI16 | 103 ; CHECK-LABEL: testZextI16 |
104 ; match the trunc instruction | 104 ; match the trunc instruction |
105 ; CHECK: and {{.*}},0x1 | 105 ; CHECK: and {{.*}},0x1 |
106 ; match the zext i1 instruction (note 32-bit reg is used because it's shorter). | 106 ; match the zext i1 instruction (note 32-bit reg is used because it's shorter). |
107 ; CHECK: movzx [[REG:e.*]],{{[a-d]l|BYTE PTR}} | 107 ; CHECK: movzx [[REG:e.*]],{{[a-d]l|BYTE PTR}} |
108 ; CHECK: and [[REG]],0x1 | 108 ; CHECK-NOT: and [[REG]],0x1 |
109 | 109 |
110 ; ARM32-LABEL: testZextI16 | 110 ; ARM32-LABEL: testZextI16 |
111 ; match the trunc instruction | 111 ; match the trunc instruction |
112 ; ARM32: and {{.*}}, #1 | 112 ; ARM32: and {{.*}}, #1 |
113 ; match the zext (no need to uxt into a reg if src is already in a reg) | 113 ; match the zext (no need to uxt into a reg if src is already in a reg) |
114 ; ARM32: and {{.*}}, #1 | 114 ; ARM32: and {{.*}}, #1 |
115 | 115 |
116 ; Test zext to i32. | 116 ; Test zext to i32. |
117 define internal i32 @testZextI32(i32 %arg) { | 117 define internal i32 @testZextI32(i32 %arg) { |
118 entry: | 118 entry: |
119 %arg_i1 = trunc i32 %arg to i1 | 119 %arg_i1 = trunc i32 %arg to i1 |
120 %result_i32 = zext i1 %arg_i1 to i32 | 120 %result_i32 = zext i1 %arg_i1 to i32 |
121 ret i32 %result_i32 | 121 ret i32 %result_i32 |
122 } | 122 } |
123 ; CHECK-LABEL: testZextI32 | 123 ; CHECK-LABEL: testZextI32 |
124 ; match the trunc instruction | 124 ; match the trunc instruction |
125 ; CHECK: and {{.*}},0x1 | 125 ; CHECK: and {{.*}},0x1 |
126 ; match the zext i1 instruction | 126 ; match the zext i1 instruction |
127 ; CHECK: movzx | 127 ; CHECK: movzx |
128 ; CHECK: and {{.*}},0x1 | 128 ; CHECK-NOT: and {{.*}},0x1 |
129 ; ARM32-LABEL: testZextI32 | 129 ; ARM32-LABEL: testZextI32 |
130 ; ARM32: and {{.*}}, #1 | 130 ; ARM32: and {{.*}}, #1 |
131 ; ARM32: and {{.*}}, #1 | 131 ; ARM32: and {{.*}}, #1 |
132 | 132 |
133 ; Test zext to i64. | 133 ; Test zext to i64. |
134 define internal i64 @testZextI64(i32 %arg) { | 134 define internal i64 @testZextI64(i32 %arg) { |
135 entry: | 135 entry: |
136 %arg_i1 = trunc i32 %arg to i1 | 136 %arg_i1 = trunc i32 %arg to i1 |
137 %result_i64 = zext i1 %arg_i1 to i64 | 137 %result_i64 = zext i1 %arg_i1 to i64 |
138 ret i64 %result_i64 | 138 ret i64 %result_i64 |
139 } | 139 } |
140 ; CHECK-LABEL: testZextI64 | 140 ; CHECK-LABEL: testZextI64 |
141 ; match the trunc instruction | 141 ; match the trunc instruction |
142 ; CHECK: and {{.*}},0x1 | 142 ; CHECK: and {{.*}},0x1 |
143 ; match the zext i1 instruction | 143 ; match the zext i1 instruction |
144 ; CHECK: movzx | 144 ; CHECK: movzx |
145 ; CHECK: and {{.*}},0x1 | |
146 ; CHECK: mov {{.*}},0x0 | 145 ; CHECK: mov {{.*}},0x0 |
147 ; ARM32-LABEL: testZextI64 | 146 ; ARM32-LABEL: testZextI64 |
148 ; ARM32: and {{.*}}, #1 | 147 ; ARM32: and {{.*}}, #1 |
149 ; ARM32: and {{.*}}, #1 | 148 ; ARM32: and {{.*}}, #1 |
150 ; ARM32: mov {{.*}}, #0 | 149 ; ARM32: mov {{.*}}, #0 |
151 | 150 |
152 ; Test sext to i8. | 151 ; Test sext to i8. |
153 define internal i32 @testSextI8(i32 %arg) { | 152 define internal i32 @testSextI8(i32 %arg) { |
154 entry: | 153 entry: |
155 %arg_i1 = trunc i32 %arg to i1 | 154 %arg_i1 = trunc i32 %arg to i1 |
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250 ; ARM32: mov{{.*}}, #1 | 249 ; ARM32: mov{{.*}}, #1 |
251 ; ARM32: lsl | 250 ; ARM32: lsl |
252 ; ARM32: asr | 251 ; ARM32: asr |
253 | 252 |
254 define internal i32 @testZextTrue() { | 253 define internal i32 @testZextTrue() { |
255 %result = zext i1 true to i32 | 254 %result = zext i1 true to i32 |
256 ret i32 %result | 255 ret i32 %result |
257 } | 256 } |
258 ; CHECK-LABEL: testZextTrue | 257 ; CHECK-LABEL: testZextTrue |
259 ; CHECK: movzx | 258 ; CHECK: movzx |
260 ; CHECK: and {{.*}},0x1 | 259 ; CHECK-NOT: and {{.*}},0x1 |
261 ; ARM32-LABEL: testZextTrue | 260 ; ARM32-LABEL: testZextTrue |
262 ; ARM32: mov{{.*}}, #1 | 261 ; ARM32: mov{{.*}}, #1 |
263 ; ARM32: and {{.*}}, #1 | 262 ; ARM32: and {{.*}}, #1 |
264 | 263 |
265 ; Test fptosi float to i1. | 264 ; Test fptosi float to i1. |
266 define internal i32 @testFptosiFloat(float %arg) { | 265 define internal i32 @testFptosiFloat(float %arg) { |
267 entry: | 266 entry: |
268 %arg_i1 = fptosi float %arg to i1 | 267 %arg_i1 = fptosi float %arg to i1 |
269 %result = sext i1 %arg_i1 to i32 | 268 %result = sext i1 %arg_i1 to i32 |
270 ret i32 %result | 269 ret i32 %result |
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282 %arg_i1 = fptosi double %arg to i1 | 281 %arg_i1 = fptosi double %arg to i1 |
283 %result = sext i1 %arg_i1 to i32 | 282 %result = sext i1 %arg_i1 to i32 |
284 ret i32 %result | 283 ret i32 %result |
285 } | 284 } |
286 ; CHECK-LABEL: testFptosiDouble | 285 ; CHECK-LABEL: testFptosiDouble |
287 ; CHECK: cvttsd2si | 286 ; CHECK: cvttsd2si |
288 ; CHECK: and {{.*}},0x1 | 287 ; CHECK: and {{.*}},0x1 |
289 ; CHECK: movzx [[REG:.*]], | 288 ; CHECK: movzx [[REG:.*]], |
290 ; CHECK-NEXT: shl [[REG]],0x1f | 289 ; CHECK-NEXT: shl [[REG]],0x1f |
291 ; CHECK-NEXT: sar [[REG]],0x1f | 290 ; CHECK-NEXT: sar [[REG]],0x1f |
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