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1 ; This tries to be a comprehensive test of f32 and f64 convert operations. | 1 ; This tries to be a comprehensive test of f32 and f64 convert operations. |
2 ; The CHECK lines are only checking for basic instruction patterns | 2 ; The CHECK lines are only checking for basic instruction patterns |
3 ; that should be present regardless of the optimization level, so | 3 ; that should be present regardless of the optimization level, so |
4 ; there are no special OPTM1 match lines. | 4 ; there are no special OPTM1 match lines. |
5 | 5 |
6 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s | 6 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s |
7 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s | 7 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s |
8 | 8 |
9 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ | 9 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ |
10 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ | 10 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ |
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249 ; ARM32: uxtb | 249 ; ARM32: uxtb |
250 | 250 |
251 define internal i32 @doubleToUnsigned1(double %a) { | 251 define internal i32 @doubleToUnsigned1(double %a) { |
252 entry: | 252 entry: |
253 %tobool = fptoui double %a to i1 | 253 %tobool = fptoui double %a to i1 |
254 %tobool.ret_ext = zext i1 %tobool to i32 | 254 %tobool.ret_ext = zext i1 %tobool to i32 |
255 ret i32 %tobool.ret_ext | 255 ret i32 %tobool.ret_ext |
256 } | 256 } |
257 ; CHECK-LABEL: doubleToUnsigned1 | 257 ; CHECK-LABEL: doubleToUnsigned1 |
258 ; CHECK: cvttsd2si | 258 ; CHECK: cvttsd2si |
259 ; CHECK: and eax,0x1 | 259 ; CHECK-NOT: and eax,0x1 |
260 ; ARM32-LABEL: doubleToUnsigned1 | 260 ; ARM32-LABEL: doubleToUnsigned1 |
261 ; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} | 261 ; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}} |
262 ; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]] | 262 ; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]] |
263 ; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1 | 263 ; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1 |
264 ; ARM32-NOT: uxth | 264 ; ARM32-NOT: uxth |
265 ; ARM32-NOT: uxtb | 265 ; ARM32-NOT: uxtb |
266 | 266 |
267 define internal i32 @floatToUnsigned1(float %a) { | 267 define internal i32 @floatToUnsigned1(float %a) { |
268 entry: | 268 entry: |
269 %tobool = fptoui float %a to i1 | 269 %tobool = fptoui float %a to i1 |
270 %tobool.ret_ext = zext i1 %tobool to i32 | 270 %tobool.ret_ext = zext i1 %tobool to i32 |
271 ret i32 %tobool.ret_ext | 271 ret i32 %tobool.ret_ext |
272 } | 272 } |
273 ; CHECK-LABEL: floatToUnsigned1 | 273 ; CHECK-LABEL: floatToUnsigned1 |
274 ; CHECK: cvttss2si | 274 ; CHECK: cvttss2si |
275 ; CHECK: and eax,0x1 | 275 ; CHECK-NOT: and eax,0x1 |
276 ; ARM32-LABEL: floatToUnsigned1 | 276 ; ARM32-LABEL: floatToUnsigned1 |
277 ; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}} | 277 ; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}} |
278 ; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]] | 278 ; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]] |
279 ; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1 | 279 ; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1 |
280 ; ARM32-NOT: uxth | 280 ; ARM32-NOT: uxth |
281 ; ARM32-NOT: uxtb | 281 ; ARM32-NOT: uxtb |
282 | 282 |
283 define internal double @signed64ToDouble(i64 %a) { | 283 define internal double @signed64ToDouble(i64 %a) { |
284 entry: | 284 entry: |
285 %conv = sitofp i64 %a to double | 285 %conv = sitofp i64 %a to double |
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588 %conv = bitcast i64 9035768 to double | 588 %conv = bitcast i64 9035768 to double |
589 ret double %conv | 589 ret double %conv |
590 } | 590 } |
591 ; CHECK-LABEL: int64BitcastToDoubleConst | 591 ; CHECK-LABEL: int64BitcastToDoubleConst |
592 ; CHECK: mov | 592 ; CHECK: mov |
593 ; ARM32-LABEL: int64BitcastToDoubleConst | 593 ; ARM32-LABEL: int64BitcastToDoubleConst |
594 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336 | 594 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336 |
595 ; ARM32-DAG: movt [[REG0]], #137 | 595 ; ARM32-DAG: movt [[REG0]], #137 |
596 ; ARM32-DAG: mov [[REG1:r[0-9]+]], #0 | 596 ; ARM32-DAG: mov [[REG1:r[0-9]+]], #0 |
597 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]] | 597 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]] |
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