Subzero: Don't "and" i1 values with 1.

tests_lit/llvm2ice_tests/fp.convert.ll

 ; This tries to be a comprehensive test of f32 and f64 convert operations.
 ; The CHECK lines are only checking for basic instruction patterns
 ; that should be present regardless of the optimization level, so
 ; there are no special OPTM1 match lines.
 
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
 
 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
 ; RUN:   --target arm32 -i %s --args -O2 --skip-unimplemented \
@@ skipping 238 matching lines @@
 ; ARM32: uxtb
 
 define internal i32 @doubleToUnsigned1(double %a) {
 entry:
   %tobool = fptoui double %a to i1
   %tobool.ret_ext = zext i1 %tobool to i32
   ret i32 %tobool.ret_ext
 }
 ; CHECK-LABEL: doubleToUnsigned1
 ; CHECK: cvttsd2si
-; CHECK: and eax,0x1
+; CHECK-NOT: and eax,0x1
 ; ARM32-LABEL: doubleToUnsigned1
 ; ARM32-DAG: vcvt.u32.f64 [[REG:s[0-9]*]], {{d[0-9]*}}
 ; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]]
 ; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1
 ; ARM32-NOT: uxth
 ; ARM32-NOT: uxtb
 
 define internal i32 @floatToUnsigned1(float %a) {
 entry:
   %tobool = fptoui float %a to i1
   %tobool.ret_ext = zext i1 %tobool to i32
   ret i32 %tobool.ret_ext
 }
 ; CHECK-LABEL: floatToUnsigned1
 ; CHECK: cvttss2si
-; CHECK: and eax,0x1
+; CHECK-NOT: and eax,0x1
 ; ARM32-LABEL: floatToUnsigned1
 ; ARM32-DAG: vcvt.u32.f32 [[REG:s[0-9]*]], {{s[0-9]*}}
 ; ARM32-DAG: vmov [[RES:r[0-9]+]], [[REG]]
 ; ARM32-DAG: and {{r[0-9]+}}, [[RES]], #1
 ; ARM32-NOT: uxth
 ; ARM32-NOT: uxtb
 
 define internal double @signed64ToDouble(i64 %a) {
 entry:
   %conv = sitofp i64 %a to double
@@ skipping 302 matching lines @@
   %conv = bitcast i64 9035768 to double
   ret double %conv
 }
 ; CHECK-LABEL: int64BitcastToDoubleConst
 ; CHECK: mov
 ; ARM32-LABEL: int64BitcastToDoubleConst
 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336
 ; ARM32-DAG: movt [[REG0]], #137
 ; ARM32-DAG: mov [[REG1:r[0-9]+]], #0
 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]