Subzero: Don't "and" i1 values with 1.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 2029 matching lines @@
       // t1=movzx src; dst.lo=t1; dst.hi=0
       Constant *Zero = Ctx->getConstantZero(IceType_i32);
       Variable *DestLo = llvm::cast<Variable>(loOperand(Dest));
       Variable *DestHi = llvm::cast<Variable>(hiOperand(Dest));
       Variable *Tmp = makeReg(DestLo->getType());
       if (Src0RM->getType() == IceType_i32) {
         _mov(Tmp, Src0RM);
       } else {
         _movzx(Tmp, Src0RM);
       }
-      if (Src0RM->getType() == IceType_i1) {

[John, 2015/10/09 12:14:08]

are you 100% sure this is OK? I've wondered about this for a long time, but
given that llc does something similar, I stopped thinking about it.

[Jim Stichnoth, 2015/10/09 13:50:22]

I'm about 99.44% sure...

The idea is to look through all operations that produce an i1 result and verify
that they all produce an 8-bit 0 or 1 (assuming any i1 inputs are also 0 or 1). 
For i1 arithmetic instructions, only add/or/xor are allowed, which is fine. 
Load is not allowed.  The trunc to i1 instruction still does "and 1".  So do
fptoui and fptosi.  Icmp and fcmp both do set<cc> instructions which result in 0
or 1.  So I think we're OK.

FWIW, the cross tests and spec2k are OK with this, which is what elevates my
confidence from 99% to 99.44%.

-        Constant *One = Ctx->getConstantInt32(1);
-        _and(Tmp, One);
-      }
       _mov(DestLo, Tmp);
       _mov(DestHi, Zero);
     } else if (Src0RM->getType() == IceType_i1) {
-      // t = Src0RM; t &= 1; Dest = t
-      Constant *One = Ctx->getConstantInt32(1);
+      // t = Src0RM; Dest = t
       Type DestTy = Dest->getType();
       Variable *T = nullptr;
       if (DestTy == IceType_i8) {
         _mov(T, Src0RM);
       } else {
         assert(DestTy != IceType_i1);
         assert(Traits::Is64Bit || DestTy != IceType_i64);
         // Use 32-bit for both 16-bit and 32-bit, since 32-bit ops are shorter.
         // In x86-64 we need to widen T to 64-bits to ensure that T -- if
         // written to the stack (i.e., in -Om1) will be fully zero-extended.
         T = makeReg(DestTy == IceType_i64 ? IceType_i64 : IceType_i32);
         _movzx(T, Src0RM);
       }
-      _and(T, One);
       _mov(Dest, T);
     } else {
       // t1 = movzx src; dst = t1
       Variable *T = makeReg(Dest->getType());
       _movzx(T, Src0RM);
       _mov(Dest, T);
     }
     break;
   }
   case InstCast::Trunc: {
@@ skipping 3432 matching lines @@
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H