[arm64] Fix some signed/unsigned type inconsistencies.

src/arm64/assembler-arm64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #ifndef V8_ARM64_ASSEMBLER_ARM64_H_
 #define V8_ARM64_ASSEMBLER_ARM64_H_
 
 #include <deque>
 #include <list>
 #include <map>
@@ skipping 63 matching lines @@
 
   enum RegisterType {
     // The kInvalid value is used to detect uninitialized static instances,
     // which are always zero-initialized before any constructors are called.
     kInvalid = 0,
     kRegister,
     kFPRegister,
     kNoRegister
   };
 
-  static CPURegister Create(unsigned code, unsigned size, RegisterType type) {
+  static CPURegister Create(int code, int size, RegisterType type) {
     CPURegister r = {code, size, type};
     return r;
   }
 
-  unsigned code() const;
+  int code() const;
   RegisterType type() const;
   RegList Bit() const;
-  unsigned SizeInBits() const;
+  int SizeInBits() const;
   int SizeInBytes() const;
   bool Is32Bits() const;
   bool Is64Bits() const;
   bool IsValid() const;
   bool IsValidOrNone() const;
   bool IsValidRegister() const;
   bool IsValidFPRegister() const;
   bool IsNone() const;
   bool Is(const CPURegister& other) const;
   bool Aliases(const CPURegister& other) const;
 
   bool IsZero() const;
   bool IsSP() const;
 
   bool IsRegister() const;
   bool IsFPRegister() const;
 
   Register X() const;
   Register W() const;
   FPRegister D() const;
   FPRegister S() const;
 
   bool IsSameSizeAndType(const CPURegister& other) const;
 
   // V8 compatibility.
   bool is(const CPURegister& other) const { return Is(other); }
   bool is_valid() const { return IsValid(); }
 
-  unsigned reg_code;
-  unsigned reg_size;
+  int reg_code;
+  int reg_size;
   RegisterType reg_type;
 };
 
 
 struct Register : public CPURegister {
-  static Register Create(unsigned code, unsigned size) {
+  static Register Create(int code, int size) {
     return Register(CPURegister::Create(code, size, CPURegister::kRegister));
   }
 
   Register() {
     reg_code = 0;
     reg_size = 0;
     reg_type = CPURegister::kNoRegister;
   }
 
   explicit Register(const CPURegister& r) {
@@ skipping 54 matching lines @@
 
 struct FPRegister : public CPURegister {
   enum Code {
 #define REGISTER_CODE(R) kCode_##R,
     DOUBLE_REGISTERS(REGISTER_CODE)
 #undef REGISTER_CODE
         kAfterLast,
     kCode_no_reg = -1
   };
 
-  static FPRegister Create(unsigned code, unsigned size) {
+  static FPRegister Create(int code, int size) {
     return FPRegister(
         CPURegister::Create(code, size, CPURegister::kFPRegister));
   }
 
   FPRegister() {
     reg_code = 0;
     reg_size = 0;
     reg_type = CPURegister::kNoRegister;
   }
 
@@ skipping 164 matching lines @@
   explicit CPURegList(CPURegister reg1,
                       CPURegister reg2 = NoCPUReg,
                       CPURegister reg3 = NoCPUReg,
                       CPURegister reg4 = NoCPUReg)
       : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
         size_(reg1.SizeInBits()), type_(reg1.type()) {
     DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
     DCHECK(IsValid());
   }
 
-  CPURegList(CPURegister::RegisterType type, unsigned size, RegList list)
+  CPURegList(CPURegister::RegisterType type, int size, RegList list)
       : list_(list), size_(size), type_(type) {
     DCHECK(IsValid());
   }
 
-  CPURegList(CPURegister::RegisterType type, unsigned size,
-             unsigned first_reg, unsigned last_reg)
+  CPURegList(CPURegister::RegisterType type, int size, int first_reg,
+             int last_reg)
       : size_(size), type_(type) {
     DCHECK(((type == CPURegister::kRegister) &&
             (last_reg < kNumberOfRegisters)) ||
            ((type == CPURegister::kFPRegister) &&
             (last_reg < kNumberOfFPRegisters)));
     DCHECK(last_reg >= first_reg);
     list_ = (1UL << (last_reg + 1)) - 1;
     list_ &= ~((1UL << first_reg) - 1);
     DCHECK(IsValid());
   }
@@ skipping 36 matching lines @@
   void Remove(int code);
 
   // Remove all callee-saved registers from the list. This can be useful when
   // preparing registers for an AAPCS64 function call, for example.
   void RemoveCalleeSaved();
 
   CPURegister PopLowestIndex();
   CPURegister PopHighestIndex();
 
   // AAPCS64 callee-saved registers.
-  static CPURegList GetCalleeSaved(unsigned size = kXRegSizeInBits);
-  static CPURegList GetCalleeSavedFP(unsigned size = kDRegSizeInBits);
+  static CPURegList GetCalleeSaved(int size = kXRegSizeInBits);
+  static CPURegList GetCalleeSavedFP(int size = kDRegSizeInBits);
 
   // AAPCS64 caller-saved registers. Note that this includes lr.
-  static CPURegList GetCallerSaved(unsigned size = kXRegSizeInBits);
-  static CPURegList GetCallerSavedFP(unsigned size = kDRegSizeInBits);
+  static CPURegList GetCallerSaved(int size = kXRegSizeInBits);
+  static CPURegList GetCallerSavedFP(int size = kDRegSizeInBits);
 
   // Registers saved as safepoints.
   static CPURegList GetSafepointSavedRegisters();
 
   bool IsEmpty() const {
     DCHECK(IsValid());
     return list_ == 0;
   }
 
   bool IncludesAliasOf(const CPURegister& other1,
                        const CPURegister& other2 = NoCPUReg,
                        const CPURegister& other3 = NoCPUReg,
                        const CPURegister& other4 = NoCPUReg) const {
     DCHECK(IsValid());
     RegList list = 0;
     if (!other1.IsNone() && (other1.type() == type_)) list |= other1.Bit();
     if (!other2.IsNone() && (other2.type() == type_)) list |= other2.Bit();
     if (!other3.IsNone() && (other3.type() == type_)) list |= other3.Bit();
     if (!other4.IsNone() && (other4.type() == type_)) list |= other4.Bit();
     return (list_ & list) != 0;
   }
 
   int Count() const {
     DCHECK(IsValid());
     return CountSetBits(list_, kRegListSizeInBits);
   }
 
-  unsigned RegisterSizeInBits() const {
+  int RegisterSizeInBits() const {
     DCHECK(IsValid());
     return size_;
   }
 
-  unsigned RegisterSizeInBytes() const {
+  int RegisterSizeInBytes() const {
     int size_in_bits = RegisterSizeInBits();
     DCHECK((size_in_bits % kBitsPerByte) == 0);
     return size_in_bits / kBitsPerByte;
   }
 
-  unsigned TotalSizeInBytes() const {
+  int TotalSizeInBytes() const {
     DCHECK(IsValid());
     return RegisterSizeInBytes() * Count();
   }
 
  private:
   RegList list_;
-  unsigned size_;
+  int size_;
   CPURegister::RegisterType type_;
 
   bool IsValid() const {
     const RegList kValidRegisters = 0x8000000ffffffff;
     const RegList kValidFPRegisters = 0x0000000ffffffff;
     switch (type_) {
       case CPURegister::kRegister:
         return (list_ & kValidRegisters) == list_;
       case CPURegister::kFPRegister:
         return (list_ & kValidFPRegisters) == list_;
@@ skipping 601 matching lines @@
   void lsrv(const Register& rd, const Register& rn, const Register& rm);
 
   // Arithmetic shift right variable.
   void asrv(const Register& rd, const Register& rn, const Register& rm);
 
   // Rotate right variable.
   void rorv(const Register& rd, const Register& rn, const Register& rm);
 
   // Bitfield instructions.
   // Bitfield move.
-  void bfm(const Register& rd,
-           const Register& rn,
-           unsigned immr,
-           unsigned imms);
+  void bfm(const Register& rd, const Register& rn, int immr, int imms);
 
   // Signed bitfield move.
-  void sbfm(const Register& rd,
-            const Register& rn,
-            unsigned immr,
-            unsigned imms);
+  void sbfm(const Register& rd, const Register& rn, int immr, int imms);
 
   // Unsigned bitfield move.
-  void ubfm(const Register& rd,
-            const Register& rn,
-            unsigned immr,
-            unsigned imms);
+  void ubfm(const Register& rd, const Register& rn, int immr, int imms);
 
   // Bfm aliases.
   // Bitfield insert.
-  void bfi(const Register& rd,
-           const Register& rn,
-           unsigned lsb,
-           unsigned width) {
+  void bfi(const Register& rd, const Register& rn, int lsb, int width) {
     DCHECK(width >= 1);
     DCHECK(lsb + width <= rn.SizeInBits());
     bfm(rd, rn, (rd.SizeInBits() - lsb) & (rd.SizeInBits() - 1), width - 1);
   }
 
   // Bitfield extract and insert low.
-  void bfxil(const Register& rd,
-             const Register& rn,
-             unsigned lsb,
-             unsigned width) {
+  void bfxil(const Register& rd, const Register& rn, int lsb, int width) {
     DCHECK(width >= 1);
     DCHECK(lsb + width <= rn.SizeInBits());
     bfm(rd, rn, lsb, lsb + width - 1);
   }
 
   // Sbfm aliases.
   // Arithmetic shift right.
-  void asr(const Register& rd, const Register& rn, unsigned shift) {
+  void asr(const Register& rd, const Register& rn, int shift) {
     DCHECK(shift < rd.SizeInBits());
     sbfm(rd, rn, shift, rd.SizeInBits() - 1);
   }
 
   // Signed bitfield insert in zero.
-  void sbfiz(const Register& rd,
-             const Register& rn,
-             unsigned lsb,
-             unsigned width) {
+  void sbfiz(const Register& rd, const Register& rn, int lsb, int width) {
     DCHECK(width >= 1);
     DCHECK(lsb + width <= rn.SizeInBits());
     sbfm(rd, rn, (rd.SizeInBits() - lsb) & (rd.SizeInBits() - 1), width - 1);
   }
 
   // Signed bitfield extract.
-  void sbfx(const Register& rd,
-            const Register& rn,
-            unsigned lsb,
-            unsigned width) {
+  void sbfx(const Register& rd, const Register& rn, int lsb, int width) {
     DCHECK(width >= 1);
     DCHECK(lsb + width <= rn.SizeInBits());
     sbfm(rd, rn, lsb, lsb + width - 1);
   }
 
   // Signed extend byte.
   void sxtb(const Register& rd, const Register& rn) {
     sbfm(rd, rn, 0, 7);
   }
 
   // Signed extend halfword.
   void sxth(const Register& rd, const Register& rn) {
     sbfm(rd, rn, 0, 15);
   }
 
   // Signed extend word.
   void sxtw(const Register& rd, const Register& rn) {
     sbfm(rd, rn, 0, 31);
   }
 
   // Ubfm aliases.
   // Logical shift left.
-  void lsl(const Register& rd, const Register& rn, unsigned shift) {
-    unsigned reg_size = rd.SizeInBits();
+  void lsl(const Register& rd, const Register& rn, int shift) {
+    int reg_size = rd.SizeInBits();
     DCHECK(shift < reg_size);
     ubfm(rd, rn, (reg_size - shift) % reg_size, reg_size - shift - 1);
   }
 
   // Logical shift right.
-  void lsr(const Register& rd, const Register& rn, unsigned shift) {
+  void lsr(const Register& rd, const Register& rn, int shift) {
     DCHECK(shift < rd.SizeInBits());
     ubfm(rd, rn, shift, rd.SizeInBits() - 1);
   }
 
   // Unsigned bitfield insert in zero.
-  void ubfiz(const Register& rd,
-             const Register& rn,
-             unsigned lsb,
-             unsigned width) {
+  void ubfiz(const Register& rd, const Register& rn, int lsb, int width) {
     DCHECK(width >= 1);
     DCHECK(lsb + width <= rn.SizeInBits());
     ubfm(rd, rn, (rd.SizeInBits() - lsb) & (rd.SizeInBits() - 1), width - 1);
   }
 
   // Unsigned bitfield extract.
-  void ubfx(const Register& rd,
-            const Register& rn,
-            unsigned lsb,
-            unsigned width) {
+  void ubfx(const Register& rd, const Register& rn, int lsb, int width) {
     DCHECK(width >= 1);
     DCHECK(lsb + width <= rn.SizeInBits());
     ubfm(rd, rn, lsb, lsb + width - 1);
   }
 
   // Unsigned extend byte.
   void uxtb(const Register& rd, const Register& rn) {
     ubfm(rd, rn, 0, 7);
   }
 
   // Unsigned extend halfword.
   void uxth(const Register& rd, const Register& rn) {
     ubfm(rd, rn, 0, 15);
   }
 
   // Unsigned extend word.
   void uxtw(const Register& rd, const Register& rn) {
     ubfm(rd, rn, 0, 31);
   }
 
   // Extract.
-  void extr(const Register& rd,
-            const Register& rn,
-            const Register& rm,
-            unsigned lsb);
+  void extr(const Register& rd, const Register& rn, const Register& rm,
+            int lsb);
 
   // Conditional select: rd = cond ? rn : rm.
   void csel(const Register& rd,
             const Register& rn,
             const Register& rm,
             Condition cond);
 
   // Conditional select increment: rd = cond ? rn : rm + 1.
   void csinc(const Register& rd,
              const Register& rn,
@@ skipping 949 matching lines @@
  public:
   explicit EnsureSpace(Assembler* assembler) {
     assembler->CheckBufferSpace();
   }
 };
 
 }  // namespace internal
 }  // namespace v8
 
 #endif  // V8_ARM64_ASSEMBLER_ARM64_H_