Subzero: Consider all instruction variables for register preference.

src/IceInst.cpp

 //===- subzero/src/IceInst.cpp - High-level instruction implementation ----===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 231 matching lines @@
 
 bool InstArithmetic::isCommutative() const {
   return InstArithmeticAttributes[getOp()].IsCommutative;
 }
 
 InstAssign::InstAssign(Cfg *Func, Variable *Dest, Operand *Source)
     : InstHighLevel(Func, Inst::Assign, 1, Dest) {
   addSource(Source);
 }
 
+bool InstAssign::isVarAssign() const { return llvm::isa<Variable>(getSrc(0)); }
+
 // If TargetTrue==TargetFalse, we turn it into an unconditional branch. This
 // ensures that, along with the 'switch' instruction semantics, there is at
 // most one edge from one node to another.
 InstBr::InstBr(Cfg *Func, Operand *Source, CfgNode *TargetTrue_,
                CfgNode *TargetFalse_)
     : InstHighLevel(Func, Inst::Br, 1, nullptr), TargetFalse(TargetFalse_),
       TargetTrue(TargetTrue_) {
   if (TargetTrue == TargetFalse) {
     TargetTrue = nullptr; // turn into unconditional version
   } else {
@@ skipping 691 matching lines @@
     // upper 32 bits of rax. We need to recognize and preserve these.
     return true;
   }
   if (!Dest->hasReg() && !SrcVar->hasReg() &&
       Dest->getStackOffset() == SrcVar->getStackOffset())
     return true;
   return false;
 }
 
 } // end of namespace Ice