[turbofan] Create ExplicitOperands to specify operands without virtual registers

src/compiler/instruction.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/common-operator.h"
 #include "src/compiler/graph.h"
 #include "src/compiler/instruction.h"
 #include "src/compiler/schedule.h"
 
 namespace v8 {
@@ skipping 87 matching lines @@
                 << "]";
     case InstructionOperand::IMMEDIATE: {
       auto imm = ImmediateOperand::cast(op);
       switch (imm.type()) {
         case ImmediateOperand::INLINE:
           return os << "#" << imm.inline_value();
         case ImmediateOperand::INDEXED:
           return os << "[immediate:" << imm.indexed_value() << "]";
       }
     }
+    case InstructionOperand::EXPLICIT:
     case InstructionOperand::ALLOCATED: {
-      auto allocated = AllocatedOperand::cast(op);
-      switch (allocated.allocated_kind()) {
-        case AllocatedOperand::STACK_SLOT:
-          os << "[stack:" << StackSlotOperand::cast(op).index();
-          break;
-        case AllocatedOperand::DOUBLE_STACK_SLOT:
-          os << "[double_stack:" << DoubleStackSlotOperand::cast(op).index();
-          break;
-        case AllocatedOperand::REGISTER:
-          os << "[" << RegisterOperand::cast(op).GetRegister().ToString()
-             << "|R";
-          break;
-        case AllocatedOperand::DOUBLE_REGISTER:
-          os << "["
-             << DoubleRegisterOperand::cast(op).GetDoubleRegister().ToString()
-             << "|R";
-          break;
+      auto allocated = LocationOperand::cast(op);
+      if (op.IsStackSlot()) {
+        os << "[stack:" << LocationOperand::cast(op).index();
+      } else if (op.IsDoubleStackSlot()) {
+        os << "[double_stack:" << LocationOperand::cast(op).index();
+      } else if (op.IsRegister()) {
+        os << "[" << LocationOperand::cast(op).GetRegister().ToString() << "|R";
+      } else {
+        DCHECK(op.IsDoubleRegister());
+        os << "[" << LocationOperand::cast(op).GetDoubleRegister().ToString()
+           << "|R";
+      }
+      if (allocated.IsExplicit()) {
+        os << "|E";
       }
       switch (allocated.machine_type()) {
         case kRepWord32:
           os << "|w32";
           break;
         case kRepWord64:
           os << "|w64";
           break;
         case kRepFloat32:
           os << "|f32";
@@ skipping 38 matching lines @@
   }
   return true;
 }
 
 
 MoveOperands* ParallelMove::PrepareInsertAfter(MoveOperands* move) const {
   MoveOperands* replacement = nullptr;
   MoveOperands* to_eliminate = nullptr;
   for (auto curr : *this) {
     if (curr->IsEliminated()) continue;
-    if (curr->destination().EqualsModuloType(move->source())) {
+    if (curr->destination().EqualsCanonicalized(move->source())) {
       DCHECK(!replacement);
       replacement = curr;
       if (to_eliminate != nullptr) break;
-    } else if (curr->destination().EqualsModuloType(move->destination())) {
+    } else if (curr->destination().EqualsCanonicalized(move->destination())) {
       DCHECK(!to_eliminate);
       to_eliminate = curr;
       if (replacement != nullptr) break;
     }
   }
   DCHECK_IMPLIES(replacement == to_eliminate, replacement == nullptr);
   if (replacement != nullptr) move->set_source(replacement->source());
   return to_eliminate;
 }
 
 
+ExplicitOperand::ExplicitOperand(LocationKind kind, MachineType machine_type,
+                                 int index)
+    : LocationOperand(EXPLICIT, kind, machine_type, index) {
+  DCHECK_IMPLIES(kind == REGISTER && !IsFloatingPoint(machine_type),
+                 Register::from_code(index).IsAllocatable());
+  DCHECK_IMPLIES(kind == REGISTER && IsFloatingPoint(machine_type),
+                 DoubleRegister::from_code(index).IsAllocatable());
+}
+
+
 Instruction::Instruction(InstructionCode opcode)
     : opcode_(opcode),
       bit_field_(OutputCountField::encode(0) | InputCountField::encode(0) |
                  TempCountField::encode(0) | IsCallField::encode(false)),
       reference_map_(NULL) {
   parallel_moves_[0] = nullptr;
   parallel_moves_[1] = nullptr;
 }
 
 
@@ skipping 46 matching lines @@
     first = false;
     PrintableMoveOperands pmo = {printable.register_configuration_, move};
     os << pmo;
   }
   return os;
 }
 
 
 void ReferenceMap::RecordReference(const AllocatedOperand& op) {
   // Do not record arguments as pointers.
-  if (op.IsStackSlot() && StackSlotOperand::cast(op).index() < 0) return;
+  if (op.IsStackSlot() && LocationOperand::cast(op).index() < 0) return;
   DCHECK(!op.IsDoubleRegister() && !op.IsDoubleStackSlot());
   reference_operands_.push_back(op);
 }
 
 
 std::ostream& operator<<(std::ostream& os, const ReferenceMap& pm) {
   os << "{";
   bool first = true;
   PrintableInstructionOperand poi = {
       RegisterConfiguration::ArchDefault(RegisterConfiguration::TURBOFAN),
@@ skipping 600 matching lines @@
       os << " B" << succ.ToInt();
     }
     os << "\n";
   }
   return os;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8