A64: Make the simulator sampling friendly.

src/a64/instructions-a64.h

 // Copyright 2013 the V8 project authors. All rights reserved.
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met:
 //
 //     * Redistributions of source code must retain the above copyright
 //       notice, this list of conditions and the following disclaimer.
 //     * Redistributions in binary form must reproduce the above
 //       copyright notice, this list of conditions and the following
 //       disclaimer in the documentation and/or other materials provided
@@ skipping 195 matching lines @@
   }
 
   bool IsAddSubImmediate() const {
     return Mask(AddSubImmediateFMask) == AddSubImmediateFixed;
   }
 
   bool IsAddSubExtended() const {
     return Mask(AddSubExtendedFMask) == AddSubExtendedFixed;
   }
 
+  // Match any loads or stores, including pairs.
   bool IsLoadOrStore() const {
     return Mask(LoadStoreAnyFMask) == LoadStoreAnyFixed;
   }
 
+  // Match any loads, including pairs.
+  bool IsLoad() const;
+  // Match any stores, including pairs.
+  bool IsStore() const;
+
   // Indicate whether Rd can be the stack pointer or the zero register. This
   // does not check that the instruction actually has an Rd field.
   Reg31Mode RdMode() const {
     // The following instructions use csp or wsp as Rd:
     //  Add/sub (immediate) when not setting the flags.
     //  Add/sub (extended) when not setting the flags.
     //  Logical (immediate) when not setting the flags.
     // Otherwise, r31 is the zero register.
     if (IsAddSubImmediate() || IsAddSubExtended()) {
       if (Mask(AddSubSetFlagsBit)) {
@@ skipping 246 matching lines @@
   TRACE_ENABLE   = 1 << 6,
   TRACE_DISABLE  = 2 << 6,
   TRACE_OVERRIDE = 3 << 6
 };
 
 
 } }  // namespace v8::internal
 
 
 #endif  // V8_A64_INSTRUCTIONS_A64_H_