Make sure that all globals are internal, except for "start" functions.

tests_lit/llvm2ice_tests/switch-opt.ll

 ; This tests a switch statement, including multiple branches to the
 ; same label which also results in phi instructions with multiple
 ; entries for the same incoming edge.
 
 ; For x86 see adv-switch-opt.ll
 
 ; TODO(jvoung): Update to -02 once the phi assignments is done for ARM
 ; RUN: %if --need=target_ARM32 --need=allow_dump \
 ; RUN:   --command %p2i --filetype=asm --assemble --disassemble \
 ; RUN:   --target arm32 -i %s --args -Om1 --skip-unimplemented \
 ; RUN:   | %if --need=target_ARM32 --need=allow_dump \
 ; RUN:     --command FileCheck --check-prefix ARM32 %s
 
-define i32 @testSwitch(i32 %a) {
+define internal i32 @testSwitch(i32 %a) {
 entry:
   switch i32 %a, label %sw.default [
     i32 1, label %sw.epilog
     i32 2, label %sw.epilog
     i32 3, label %sw.epilog
     i32 7, label %sw.bb1
     i32 8, label %sw.bb1
     i32 15, label %sw.bb2
     i32 14, label %sw.bb2
   ]
@@ skipping 12 matching lines @@
 
 sw.epilog:                                        ; preds = %sw.bb2, %sw.default, %entry, %entry, %entry
   %result.1 = phi i32 [ %add, %sw.default ], [ %result.0, %sw.bb2 ], [ 17, %entry ], [ 17, %entry ], [ 17, %entry ]
   ret i32 %result.1
 }
 
 ; Check for a valid addressing mode when the switch operand is an
 ; immediate.  It's important that there is exactly one case, because
 ; for two or more cases the source operand is legalized into a
 ; register.
-define i32 @testSwitchImm() {
+define internal i32 @testSwitchImm() {
 entry:
   switch i32 10, label %sw.default [
     i32 1, label %sw.default
   ]
 
 sw.default:
   ret i32 20
 }
 ; ARM32-LABEL: testSwitchImm
 ; ARM32: cmp {{r[0-9]+}}, #1
@@ skipping 40 matching lines @@
 ; ARM32: movw [[REG:r[0-9]+]], #30864
 ; ARM32-NEXT: movt [[REG]], #13398
 ; ARM32-NEXT: cmp {{r[0-9]+}}, [[REG]]
 ; ARM32-NEXT: cmpeq {{r[0-9]+}}, #18
 ; ARM32-NEXT: beq
 ; ARM32-NEXT: b
 
 ; Similar to testSwitchImm, make sure proper addressing modes are
 ; used.  In reality, this is tested by running the output through the
 ; assembler.
-define i32 @testSwitchImm64() {
+define internal i32 @testSwitchImm64() {
 entry:
   switch i64 10, label %sw.default [
     i64 1, label %sw.default
   ]
 
 sw.default:
   ret i32 20
 }
 ; ARM32-LABEL: testSwitchImm64
 ; ARM32: cmp {{r[0-9]+}}, #1
 ; ARM32-NEXT: cmpeq {{r[0-9]+}}, #0
 ; ARM32-NEXT: beq [[ADDR:[0-9a-f]+]]
 ; ARM32-NEXT: b [[ADDR]]
 
-define i32 @testSwitchUndef64() {
+define internal i32 @testSwitchUndef64() {
 entry:
   switch i64 undef, label %sw.default [
     i64 1, label %sw.default
   ]
 
 sw.default:
   ret i32 20
 }
 ; ARM32-LABEL: testSwitchUndef64
 ; ARM32: movw {{.*}}, #0
 ; ARM32: movw {{.*}}, #0