Make sure that all globals are internal, except for "start" functions.

tests_lit/llvm2ice_tests/randomize-regalloc.ll

 ; This is a smoke test of randomized register allocation.  The output
 ; of this test will change with changes to the random number generator
 ; implementation.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=1 \
 ; RUN:   -randomize-regalloc \
 ; RUN:   | FileCheck %s --check-prefix=CHECK_1
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=1 \
 ; RUN:   -randomize-regalloc \
 ; RUN:   | FileCheck %s --check-prefix=OPTM1_1
 
 ; Same tests but with a different seed, just to verify randomness.
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -sz-seed=123 \
 ; RUN:   -randomize-regalloc \
 ; RUN:   | FileCheck %s --check-prefix=CHECK_123
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -sz-seed=123 \
 ; RUN:   -randomize-regalloc \
 ; RUN:   | FileCheck %s --check-prefix=OPTM1_123
 
-define <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
+define internal <4 x i32> @mul_v4i32(<4 x i32> %a, <4 x i32> %b) {
 entry:
   %res = mul <4 x i32> %a, %b
   ret <4 x i32> %res
 ; OPTM1_1-LABEL: mul_v4i32
 ; OPTM1_1: sub     esp,0x3c
 ; OPTM1_1-NEXT: movups  XMMWORD PTR [esp+0x20],xmm0
 ; OPTM1_1-NEXT: movups  XMMWORD PTR [esp+0x10],xmm1
 ; OPTM1_1-NEXT: movups  xmm0,XMMWORD PTR [esp+0x20]
 ; OPTM1_1-NEXT: pshufd  xmm7,XMMWORD PTR [esp+0x20],0x31
 ; OPTM1_1-NEXT: pshufd  xmm3,XMMWORD PTR [esp+0x10],0x31
@@ skipping 40 matching lines @@
 ; CHECK_123-NEXT: pmuludq xmm3,xmm1
 ; CHECK_123-NEXT: pmuludq xmm0,xmm5
 ; CHECK_123-NEXT: shufps  xmm3,xmm0,0x88
 ; CHECK_123-NEXT: pshufd  xmm3,xmm3,0xd8
 ; CHECK_123-NEXT: movups  xmm0,xmm3
 ; CHECK_123-NEXT: ret
 }
 
 ; ERRORS-NOT: ICE translation error
 ; DUMP-NOT: SZ