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| 1 ; This test checks that undef values are represented as zero. | 1 ; This test checks that undef values are represented as zero. |
| 2 | 2 |
| 3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ | 3 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \ |
| 4 ; RUN: | FileCheck %s | 4 ; RUN: | FileCheck %s |
| 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ | 5 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \ |
| 6 ; RUN: | FileCheck %s | 6 ; RUN: | FileCheck %s |
| 7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ | 7 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 -mattr=sse4.1 \ |
| 8 ; RUN: | FileCheck %s | 8 ; RUN: | FileCheck %s |
| 9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ | 9 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 -mattr=sse4.1 \ |
| 10 ; RUN: | FileCheck %s | 10 ; RUN: | FileCheck %s |
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| 31 ret i32 %ret | 31 ret i32 %ret |
| 32 ; CHECK-LABEL: trunc_undef_i64 | 32 ; CHECK-LABEL: trunc_undef_i64 |
| 33 ; CHECK: mov eax,0x0 | 33 ; CHECK: mov eax,0x0 |
| 34 ; CHECK: ret | 34 ; CHECK: ret |
| 35 } | 35 } |
| 36 | 36 |
| 37 define float @undef_float() { | 37 define float @undef_float() { |
| 38 entry: | 38 entry: |
| 39 ret float undef | 39 ret float undef |
| 40 ; CHECK-LABEL: undef_float | 40 ; CHECK-LABEL: undef_float |
| 41 ; CHECK: fld DWORD PTR {{.*}} .L$float$0 | 41 ; CHECK: fld DWORD PTR {{.*}} .L$float$00000000 |
| 42 } | 42 } |
| 43 | 43 |
| 44 define <4 x i1> @undef_v4i1() { | 44 define <4 x i1> @undef_v4i1() { |
| 45 entry: | 45 entry: |
| 46 ret <4 x i1> undef | 46 ret <4 x i1> undef |
| 47 ; CHECK-LABEL: undef_v4i1 | 47 ; CHECK-LABEL: undef_v4i1 |
| 48 ; CHECK: pxor | 48 ; CHECK: pxor |
| 49 } | 49 } |
| 50 | 50 |
| 51 define <8 x i1> @undef_v8i1() { | 51 define <8 x i1> @undef_v8i1() { |
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| 184 ret <4 x float> %val | 184 ret <4 x float> %val |
| 185 ; CHECK-LABEL: vector_insertelement_arg1 | 185 ; CHECK-LABEL: vector_insertelement_arg1 |
| 186 ; CHECK: pxor | 186 ; CHECK: pxor |
| 187 } | 187 } |
| 188 | 188 |
| 189 define <4 x float> @vector_insertelement_arg2(<4 x float> %arg) { | 189 define <4 x float> @vector_insertelement_arg2(<4 x float> %arg) { |
| 190 entry: | 190 entry: |
| 191 %val = insertelement <4 x float> %arg, float undef, i32 0 | 191 %val = insertelement <4 x float> %arg, float undef, i32 0 |
| 192 ret <4 x float> %val | 192 ret <4 x float> %val |
| 193 ; CHECK-LABEL: vector_insertelement_arg2 | 193 ; CHECK-LABEL: vector_insertelement_arg2 |
| 194 ; CHECK: {{movss|insertps}} {{.*}},DWORD PTR {{.*}} .L$float$0 | 194 ; CHECK: {{movss|insertps}} {{.*}},DWORD PTR {{.*}} .L$float$00000000 |
| 195 } | 195 } |
| 196 | 196 |
| 197 define float @vector_extractelement_v4f32_index_0() { | 197 define float @vector_extractelement_v4f32_index_0() { |
| 198 entry: | 198 entry: |
| 199 %val = extractelement <4 x float> undef, i32 0 | 199 %val = extractelement <4 x float> undef, i32 0 |
| 200 ret float %val | 200 ret float %val |
| 201 ; CHECK-LABEL: vector_extractelement_v4f32_index_0 | 201 ; CHECK-LABEL: vector_extractelement_v4f32_index_0 |
| 202 ; CHECK: pxor | 202 ; CHECK: pxor |
| 203 } | 203 } |
| 204 | 204 |
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| 283 ; CHECK: pxor | 283 ; CHECK: pxor |
| 284 } | 284 } |
| 285 | 285 |
| 286 define <4 x float> @vector_select_v4f32_arg2(<4 x i1> %cond, <4 x float> %a) { | 286 define <4 x float> @vector_select_v4f32_arg2(<4 x i1> %cond, <4 x float> %a) { |
| 287 entry: | 287 entry: |
| 288 %val = select <4 x i1> %cond, <4 x float> %a, <4 x float> undef | 288 %val = select <4 x i1> %cond, <4 x float> %a, <4 x float> undef |
| 289 ret <4 x float> %val | 289 ret <4 x float> %val |
| 290 ; CHECK-LABEL: vector_select_v4f32_arg2 | 290 ; CHECK-LABEL: vector_select_v4f32_arg2 |
| 291 ; CHECK: pxor | 291 ; CHECK: pxor |
| 292 } | 292 } |
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