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1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// | 1 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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248 } | 248 } |
249 /// _ldr, for all your memory to Variable data moves. It handles all types | 249 /// _ldr, for all your memory to Variable data moves. It handles all types |
250 /// (integer, floating point, and vectors.) Addr needs to be valid for Dest's | 250 /// (integer, floating point, and vectors.) Addr needs to be valid for Dest's |
251 /// type (e.g., no immediates for vector loads, and no index registers for fp | 251 /// type (e.g., no immediates for vector loads, and no index registers for fp |
252 /// loads.) | 252 /// loads.) |
253 void _ldr(Variable *Dest, OperandARM32Mem *Addr, | 253 void _ldr(Variable *Dest, OperandARM32Mem *Addr, |
254 CondARM32::Cond Pred = CondARM32::AL) { | 254 CondARM32::Cond Pred = CondARM32::AL) { |
255 Context.insert(InstARM32Ldr::create(Func, Dest, Addr, Pred)); | 255 Context.insert(InstARM32Ldr::create(Func, Dest, Addr, Pred)); |
256 } | 256 } |
257 void _ldrex(Variable *Dest, OperandARM32Mem *Addr, | 257 void _ldrex(Variable *Dest, OperandARM32Mem *Addr, |
258 CondARM32::Cond Pred = CondARM32::AL) { | 258 CondARM32::Cond Pred = CondARM32::AL) { |
259 Context.insert(InstARM32Ldrex::create(Func, Dest, Addr, Pred)); | 259 Context.insert(InstARM32Ldrex::create(Func, Dest, Addr, Pred)); |
260 if (auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest)) { | 260 if (auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest)) { |
261 Context.insert(InstFakeDef::create(Func, Dest64->getLo(), Dest)); | 261 Context.insert(InstFakeDef::create(Func, Dest64->getLo(), Dest)); |
262 Context.insert(InstFakeDef::create(Func, Dest64->getHi(), Dest)); | 262 Context.insert(InstFakeDef::create(Func, Dest64->getHi(), Dest)); |
263 } | 263 } |
264 } | 264 } |
265 void _lsl(Variable *Dest, Variable *Src0, Operand *Src1, | 265 void _lsl(Variable *Dest, Variable *Src0, Operand *Src1, |
266 CondARM32::Cond Pred = CondARM32::AL) { | 266 CondARM32::Cond Pred = CondARM32::AL) { |
267 Context.insert(InstARM32Lsl::create(Func, Dest, Src0, Src1, Pred)); | 267 Context.insert(InstARM32Lsl::create(Func, Dest, Src0, Src1, Pred)); |
268 } | 268 } |
269 void _lsr(Variable *Dest, Variable *Src0, Operand *Src1, | 269 void _lsr(Variable *Dest, Variable *Src0, Operand *Src1, |
270 CondARM32::Cond Pred = CondARM32::AL) { | 270 CondARM32::Cond Pred = CondARM32::AL) { |
271 Context.insert(InstARM32Lsr::create(Func, Dest, Src0, Src1, Pred)); | 271 Context.insert(InstARM32Lsr::create(Func, Dest, Src0, Src1, Pred)); |
272 } | 272 } |
273 void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc, | 273 void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc, |
274 CondARM32::Cond Pred = CondARM32::AL) { | 274 CondARM32::Cond Pred = CondARM32::AL) { |
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572 | 572 |
573 private: | 573 private: |
574 ~TargetHeaderARM32() = default; | 574 ~TargetHeaderARM32() = default; |
575 | 575 |
576 TargetARM32Features CPUFeatures; | 576 TargetARM32Features CPUFeatures; |
577 }; | 577 }; |
578 | 578 |
579 } // end of namespace Ice | 579 } // end of namespace Ice |
580 | 580 |
581 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H | 581 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H |
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