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Issue 138503002: Clean up ARM mov 32bit immediate code in preparation for out of line constant pool. (Closed) Base URL: https://v8.googlecode.com/svn/branches/bleeding_edge
Patch Set: Created 6 years, 9 months ago
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1 // Copyright 2011 the V8 project authors. All rights reserved. 1 // Copyright 2011 the V8 project authors. All rights reserved.
2 // Redistribution and use in source and binary forms, with or without 2 // Redistribution and use in source and binary forms, with or without
3 // modification, are permitted provided that the following conditions are 3 // modification, are permitted provided that the following conditions are
4 // met: 4 // met:
5 // 5 //
6 // * Redistributions of source code must retain the above copyright 6 // * Redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer. 7 // notice, this list of conditions and the following disclaimer.
8 // * Redistributions in binary form must reproduce the above 8 // * Redistributions in binary form must reproduce the above
9 // copyright notice, this list of conditions and the following 9 // copyright notice, this list of conditions and the following
10 // disclaimer in the documentation and/or other materials provided 10 // disclaimer in the documentation and/or other materials provided
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265 COMPARE(mvn(r6, Operand(-1), LeaveCC, ne), 265 COMPARE(mvn(r6, Operand(-1), LeaveCC, ne),
266 "13a06000 movne r6, #0"); 266 "13a06000 movne r6, #0");
267 267
268 // mov -> movw. 268 // mov -> movw.
269 if (CpuFeatures::IsSupported(ARMv7)) { 269 if (CpuFeatures::IsSupported(ARMv7)) {
270 COMPARE(mov(r5, Operand(0x01234), LeaveCC, ne), 270 COMPARE(mov(r5, Operand(0x01234), LeaveCC, ne),
271 "13015234 movwne r5, #4660"); 271 "13015234 movwne r5, #4660");
272 // We only disassemble one instruction so the eor instruction is not here. 272 // We only disassemble one instruction so the eor instruction is not here.
273 COMPARE(eor(r5, r4, Operand(0x1234), LeaveCC, ne), 273 COMPARE(eor(r5, r4, Operand(0x1234), LeaveCC, ne),
274 "1301c234 movwne ip, #4660"); 274 "1301c234 movwne ip, #4660");
275 // Movw can't do setcc so we don't get that here. Mov immediate with setcc 275 // Movw can't do setcc, so first move to ip, then the following instruction
276 // is pretty strange anyway. 276 // moves to r5. Mov immediate with setcc is pretty strange anyway.
277 COMPARE(mov(r5, Operand(0x01234), SetCC, ne), 277 COMPARE(mov(r5, Operand(0x01234), SetCC, ne),
278 "159fc000 ldrne ip, [pc, #+0]"); 278 "1301c234 movwne ip, #4660");
279 // Emit a literal pool now, otherwise this could be dumped later, in the 279 // Emit a literal pool now, otherwise this could be dumped later, in the
280 // middle of a different test. 280 // middle of a different test.
281 EMIT_PENDING_LITERALS(); 281 EMIT_PENDING_LITERALS();
282 282
283 // We only disassemble one instruction so the eor instruction is not here. 283 // We only disassemble one instruction so the eor instruction is not here.
284 // The eor does the setcc so we get a movw here. 284 // The eor does the setcc so we get a movw here.
285 COMPARE(eor(r5, r4, Operand(0x1234), SetCC, ne), 285 COMPARE(eor(r5, r4, Operand(0x1234), SetCC, ne),
286 "1301c234 movwne ip, #4660"); 286 "1301c234 movwne ip, #4660");
287 287
288 COMPARE(movt(r5, 0x4321, ne), 288 COMPARE(movt(r5, 0x4321, ne),
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893 "e16dc7ff strd ip, [sp, #-127]!"); 893 "e16dc7ff strd ip, [sp, #-127]!");
894 894
895 COMPARE(pld(MemOperand(r1, 0)), 895 COMPARE(pld(MemOperand(r1, 0)),
896 "f5d1f000 pld [r1]"); 896 "f5d1f000 pld [r1]");
897 COMPARE(pld(MemOperand(r2, 128)), 897 COMPARE(pld(MemOperand(r2, 128)),
898 "f5d2f080 pld [r2, #+128]"); 898 "f5d2f080 pld [r2, #+128]");
899 } 899 }
900 900
901 VERIFY_RUN(); 901 VERIFY_RUN();
902 } 902 }
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