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Issue 1382063002: Subzero. Adds I64 register pairs for ARM32. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: merge Created 5 years, 2 months ago
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1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 // 9 //
10 // This file defines properties of ARM32 instructions in the form of x-macros. 10 // This file defines properties of ARM32 instructions in the form of x-macros.
11 // 11 //
12 //===----------------------------------------------------------------------===// 12 //===----------------------------------------------------------------------===//
13 13
14 #ifndef SUBZERO_SRC_ICEINSTARM32_DEF 14 #ifndef SUBZERO_SRC_ICEINSTARM32_DEF
15 #define SUBZERO_SRC_ICEINSTARM32_DEF 15 #define SUBZERO_SRC_ICEINSTARM32_DEF
16 16
17 // NOTE: PC and SP are not considered isInt, to avoid register allocating. 17 // NOTE: PC and SP are not considered isInt, to avoid register allocating.
18 // 18 //
19 // For the NaCl sandbox we also need to r9 for TLS, so just reserve always. 19 // For the NaCl sandbox we also need to r9 (and the r8-r9 pair) for TLS, so
20 // TODO(jvoung): Allow r9 to be isInt when sandboxing is turned off (native 20 // just reserve always.
21 // mode). 21 // TODO(jpp): Allow r9 to be isInt when sandboxing is turned off (native mode).
22 // 22 //
23 // IP is not considered isInt to reserve it as a scratch register. A scratch 23 // IP is not considered isInt to reserve it as a scratch register. A scratch
24 // register is useful for expanding instructions post-register allocation. 24 // register is useful for expanding instructions post-register allocation.
25 // 25 //
26 // LR is not considered isInt to avoid being allocated as a register. It is 26 // LR is not considered isInt to avoid being allocated as a register. It is
27 // technically preserved, but save/restore is handled separately, based on 27 // technically preserved, but save/restore is handled separately, based on
28 // whether or not the function MaybeLeafFunc. 28 // whether or not the function MaybeLeafFunc.
29 29
30 // ALIASESn is a family of macros that we use to define register aliasing in 30 // ALIASESn is a family of macros that we use to define register aliasing in
31 // ARM32. n indicates how many aliases are being provided to the macro. It 31 // ARM32. n indicates how many aliases are being provided to the macro. It
32 // assumes the parameters are register names declared in a namespace/class 32 // assumes the parameters are register names declared in a namespace/class
33 // named RegARM32. 33 // named RegARM32.
34 #define ALIASES1(r0) \ 34 #define ALIASES1(r0) \
35 {RegARM32::r0} 35 {RegARM32::r0}
36 #define ALIASES2(r0, r1) \ 36 #define ALIASES2(r0, r1) \
37 {RegARM32::r0, RegARM32::r1} 37 {RegARM32::r0, RegARM32::r1}
38 #define ALIASES3(r0, r1, r2) \ 38 #define ALIASES3(r0, r1, r2) \
39 {RegARM32::r0, RegARM32::r1, RegARM32::r2} 39 {RegARM32::r0, RegARM32::r1, RegARM32::r2}
40 #define ALIASES4(r0, r1, r2, r3) \ 40 #define ALIASES4(r0, r1, r2, r3) \
41 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3} 41 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3}
42 #define ALIASES7(r0, r1, r2, r3, r4, r5, r6) \ 42 #define ALIASES7(r0, r1, r2, r3, r4, r5, r6) \
43 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3, RegARM32::r4, \ 43 {RegARM32::r0, RegARM32::r1, RegARM32::r2, RegARM32::r3, RegARM32::r4, \
44 RegARM32::r5,RegARM32::r6} 44 RegARM32::r5,RegARM32::r6}
45 45
46 46
47 #define REGARM32_GPR_TABLE \ 47 #define REGARM32_GPR_TABLE \
48 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 48 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
49 isInt, isFP32, isFP64, isVec128, aliases_init */ \ 49 isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init */ \
50 X(Reg_r0, 0, "r0", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r0)) \ 50 X(Reg_r0, 0, "r0", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
51 X(Reg_r1, 1, "r1", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r1)) \ 51 ALIASES2(Reg_r0, Reg_r0r1)) \
52 X(Reg_r2, 2, "r2", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r2)) \ 52 X(Reg_r1, 1, "r1", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
53 X(Reg_r3, 3, "r3", 1, 0, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r3)) \ 53 ALIASES2(Reg_r1, Reg_r0r1)) \
54 X(Reg_r4, 4, "r4", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r4)) \ 54 X(Reg_r2, 2, "r2", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
55 X(Reg_r5, 5, "r5", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r5)) \ 55 ALIASES2(Reg_r2, Reg_r2r3)) \
56 X(Reg_r6, 6, "r6", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r6)) \ 56 X(Reg_r3, 3, "r3", 1, 0, 0, 0, 1, 0, 0, 0, 0, \
57 X(Reg_r7, 7, "r7", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r7)) \ 57 ALIASES2(Reg_r3, Reg_r2r3)) \
58 X(Reg_r8, 8, "r8", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r8)) \ 58 X(Reg_r4, 4, "r4", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
59 X(Reg_r9, 9, "r9", 0, 1, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_r9)) \ 59 ALIASES2(Reg_r4, Reg_r4r5)) \
60 X(Reg_r10, 10, "r10", 0, 1, 0, 0, 1, 0, 0, 0, ALIASES1(Reg_r10)) \ 60 X(Reg_r5, 5, "r5", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
61 X(Reg_fp, 11, "fp", 0, 1, 0, 1, 1, 0, 0, 0, ALIASES1(Reg_fp)) \ 61 ALIASES2(Reg_r5, Reg_r4r5)) \
62 X(Reg_ip, 12, "ip", 1, 0, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_ip)) \ 62 X(Reg_r6, 6, "r6", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
63 X(Reg_sp, 13, "sp", 0, 0, 1, 0, 0, 0, 0, 0, ALIASES1(Reg_sp)) \ 63 ALIASES2(Reg_r6, Reg_r6r7)) \
64 X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_lr)) \ 64 X(Reg_r7, 7, "r7", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
65 X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 0, 0, 0, ALIASES1(Reg_pc)) 65 ALIASES2(Reg_r7, Reg_r6r7)) \
66 X(Reg_r8, 8, "r8", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
67 ALIASES2(Reg_r8, Reg_r8r9)) \
68 X(Reg_r9, 9, "r9", 0, 1, 0, 0, 0, 0, 0, 0, 0, \
69 ALIASES2(Reg_r9, Reg_r8r9)) \
70 X(Reg_r10, 10, "r10", 0, 1, 0, 0, 1, 0, 0, 0, 0, \
71 ALIASES2(Reg_r10, Reg_r10fp)) \
72 X(Reg_fp, 11, "fp", 0, 1, 0, 1, 1, 0, 0, 0, 0, \
73 ALIASES2(Reg_fp, Reg_r10fp)) \
74 X(Reg_ip, 12, "ip", 1, 0, 0, 0, 0, 0, 0, 0, 0, \
75 ALIASES1(Reg_ip)) \
76 X(Reg_sp, 13, "sp", 0, 0, 1, 0, 0, 0, 0, 0, 0, \
77 ALIASES1(Reg_sp)) \
78 X(Reg_lr, 14, "lr", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
79 ALIASES1(Reg_lr)) \
80 X(Reg_pc, 15, "pc", 0, 0, 0, 0, 0, 0, 0, 0, 0, \
81 ALIASES1(Reg_pc))
66 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 82 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
67 // isInt, isFP32, isFP64, isVec128, aliases_init) 83 // isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init)
84
85 // The following defines a table with the available pairs of consecutive i32
86 // GPRs starting at an even GPR that is not r14. Those are used to hold i64
87 // variables for atomic memory operations. If one of the registers in the pair
88 // is preserved, then we mark the whole pair as preserved to help the register
89 // allocator.
90 #define REGARM32_I64PAIR_TABLE \
91 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
92 isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init */ \
93 X(Reg_r0r1, 0, "r0, r1", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
94 ALIASES3(Reg_r0, Reg_r1, Reg_r0r1)) \
95 X(Reg_r2r3, 2, "r2, r3", 1, 0, 0, 0, 0, 1, 0, 0, 0, \
96 ALIASES3(Reg_r2, Reg_r3, Reg_r2r3)) \
97 X(Reg_r4r5, 4, "r4, r5", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
98 ALIASES3(Reg_r4, Reg_r5, Reg_r4r5)) \
99 X(Reg_r6r7, 6, "r6, r7", 0, 1, 0, 0, 0, 1, 0, 0, 0, \
100 ALIASES3(Reg_r6, Reg_r7, Reg_r6r7)) \
101 X(Reg_r8r9, 8, "r8, r9", 0, 1, 0, 0, 0, 0, 0, 0, 0, \
102 ALIASES3(Reg_r8, Reg_r9, Reg_r8r9)) \
103 X(Reg_r10fp, 10, "r10, fp", 0, 1, 0, 0, 0, 0, 0, 0, 0, \
104 ALIASES3(Reg_r10, Reg_fp, Reg_r10fp)) \
105 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
106 // isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init)
68 107
69 // S registers 0-15 are scratch, but 16-31 are preserved. 108 // S registers 0-15 are scratch, but 16-31 are preserved.
70 // Regenerate this with the following python script: 109 // Regenerate this with the following python script:
71 // 110 //
72 // def print_sregs(): 111 // def print_sregs():
73 // for i in xrange(0, 32): 112 // for i in xrange(0, 32):
74 // is_scratch = 1 if i < 16 else 0 113 // is_scratch = 1 if i < 16 else 0
75 // is_preserved = 1 if i >= 16 else 0 114 // is_preserved = 1 if i >= 16 else 0
76 // print (' X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' + 115 // print (' X(Reg_s{regnum:<2}, {regnum:<2}, "s{regnum}", ' +
77 // '{scratch}, {preserved}, 0, 0, 0, 1, 0, 0, ' + 116 // '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, 0, ' +
78 // 'ALIASES(Reg_s{regnum_s:<2}, Reg_d{regnum:<2}, ' + 117 // 'ALIASES(Reg_s{regnum_s:<2}, Reg_d{regnum:<2}, ' +
79 // 'Reg_q{regnum_q:<2})) \\').format( 118 // 'Reg_q{regnum_q:<2})) \\').format(
80 // regnum=i, regnum_d=i>>1, 119 // regnum=i, regnum_d=i>>1,
81 // regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved) 120 // regnum_q=i>>2, scratch=is_scratch, preserved=is_preserved)
82 // 121 //
83 // print_sregs() 122 // print_sregs()
84 // 123 //
85 #define REGARM32_FP32_TABLE \ 124 #define REGARM32_FP32_TABLE \
86 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 125 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
87 isInt, isFP32, isFP64, isVec128, aliases_init */ \ 126 isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init */ \
88 X(Reg_s0 , 0 , "s0" , 1, 0, 0, 0, 0, 1, 0, 0, \ 127 X(Reg_s0 , 0 , "s0" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
89 ALIASES3(Reg_s0 , Reg_d0 , Reg_q0)) \ 128 ALIASES3(Reg_s0 , Reg_d0 , Reg_q0)) \
90 X(Reg_s1 , 1 , "s1" , 1, 0, 0, 0, 0, 1, 0, 0, \ 129 X(Reg_s1 , 1 , "s1" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
91 ALIASES3(Reg_s1 , Reg_d0 , Reg_q0)) \ 130 ALIASES3(Reg_s1 , Reg_d0 , Reg_q0)) \
92 X(Reg_s2 , 2 , "s2" , 1, 0, 0, 0, 0, 1, 0, 0, \ 131 X(Reg_s2 , 2 , "s2" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
93 ALIASES3(Reg_s2 , Reg_d1 , Reg_q0)) \ 132 ALIASES3(Reg_s2 , Reg_d1 , Reg_q0)) \
94 X(Reg_s3 , 3 , "s3" , 1, 0, 0, 0, 0, 1, 0, 0, \ 133 X(Reg_s3 , 3 , "s3" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
95 ALIASES3(Reg_s3 , Reg_d1 , Reg_q0)) \ 134 ALIASES3(Reg_s3 , Reg_d1 , Reg_q0)) \
96 X(Reg_s4 , 4 , "s4" , 1, 0, 0, 0, 0, 1, 0, 0, \ 135 X(Reg_s4 , 4 , "s4" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
97 ALIASES3(Reg_s4 , Reg_d2 , Reg_q1)) \ 136 ALIASES3(Reg_s4 , Reg_d2 , Reg_q1)) \
98 X(Reg_s5 , 5 , "s5" , 1, 0, 0, 0, 0, 1, 0, 0, \ 137 X(Reg_s5 , 5 , "s5" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
99 ALIASES3(Reg_s5 , Reg_d2 , Reg_q1)) \ 138 ALIASES3(Reg_s5 , Reg_d2 , Reg_q1)) \
100 X(Reg_s6 , 6 , "s6" , 1, 0, 0, 0, 0, 1, 0, 0, \ 139 X(Reg_s6 , 6 , "s6" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
101 ALIASES3(Reg_s6 , Reg_d3 , Reg_q1)) \ 140 ALIASES3(Reg_s6 , Reg_d3 , Reg_q1)) \
102 X(Reg_s7 , 7 , "s7" , 1, 0, 0, 0, 0, 1, 0, 0, \ 141 X(Reg_s7 , 7 , "s7" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
103 ALIASES3(Reg_s7 , Reg_d3 , Reg_q1)) \ 142 ALIASES3(Reg_s7 , Reg_d3 , Reg_q1)) \
104 X(Reg_s8 , 8 , "s8" , 1, 0, 0, 0, 0, 1, 0, 0, \ 143 X(Reg_s8 , 8 , "s8" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
105 ALIASES3(Reg_s8 , Reg_d4 , Reg_q2)) \ 144 ALIASES3(Reg_s8 , Reg_d4 , Reg_q2)) \
106 X(Reg_s9 , 9 , "s9" , 1, 0, 0, 0, 0, 1, 0, 0, \ 145 X(Reg_s9 , 9 , "s9" , 1, 0, 0, 0, 0, 0, 1, 0, 0, \
107 ALIASES3(Reg_s9 , Reg_d4 , Reg_q2)) \ 146 ALIASES3(Reg_s9 , Reg_d4 , Reg_q2)) \
108 X(Reg_s10, 10, "s10", 1, 0, 0, 0, 0, 1, 0, 0, \ 147 X(Reg_s10, 10, "s10", 1, 0, 0, 0, 0, 0, 1, 0, 0, \
109 ALIASES3(Reg_s10, Reg_d5 , Reg_q2)) \ 148 ALIASES3(Reg_s10, Reg_d5 , Reg_q2)) \
110 X(Reg_s11, 11, "s11", 1, 0, 0, 0, 0, 1, 0, 0, \ 149 X(Reg_s11, 11, "s11", 1, 0, 0, 0, 0, 0, 1, 0, 0, \
111 ALIASES3(Reg_s11, Reg_d5 , Reg_q2)) \ 150 ALIASES3(Reg_s11, Reg_d5 , Reg_q2)) \
112 X(Reg_s12, 12, "s12", 1, 0, 0, 0, 0, 1, 0, 0, \ 151 X(Reg_s12, 12, "s12", 1, 0, 0, 0, 0, 0, 1, 0, 0, \
113 ALIASES3(Reg_s12, Reg_d6 , Reg_q3)) \ 152 ALIASES3(Reg_s12, Reg_d6 , Reg_q3)) \
114 X(Reg_s13, 13, "s13", 1, 0, 0, 0, 0, 1, 0, 0, \ 153 X(Reg_s13, 13, "s13", 1, 0, 0, 0, 0, 0, 1, 0, 0, \
115 ALIASES3(Reg_s13, Reg_d6 , Reg_q3)) \ 154 ALIASES3(Reg_s13, Reg_d6 , Reg_q3)) \
116 X(Reg_s14, 14, "s14", 1, 0, 0, 0, 0, 1, 0, 0, \ 155 X(Reg_s14, 14, "s14", 1, 0, 0, 0, 0, 0, 1, 0, 0, \
117 ALIASES3(Reg_s14, Reg_d7 , Reg_q3)) \ 156 ALIASES3(Reg_s14, Reg_d7 , Reg_q3)) \
118 X(Reg_s15, 15, "s15", 1, 0, 0, 0, 0, 1, 0, 0, \ 157 X(Reg_s15, 15, "s15", 1, 0, 0, 0, 0, 0, 1, 0, 0, \
119 ALIASES3(Reg_s15, Reg_d7 , Reg_q3)) \ 158 ALIASES3(Reg_s15, Reg_d7 , Reg_q3)) \
120 X(Reg_s16, 16, "s16", 0, 1, 0, 0, 0, 1, 0, 0, \ 159 X(Reg_s16, 16, "s16", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
121 ALIASES3(Reg_s16, Reg_d8 , Reg_q4)) \ 160 ALIASES3(Reg_s16, Reg_d8 , Reg_q4)) \
122 X(Reg_s17, 17, "s17", 0, 1, 0, 0, 0, 1, 0, 0, \ 161 X(Reg_s17, 17, "s17", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
123 ALIASES3(Reg_s17, Reg_d8 , Reg_q4)) \ 162 ALIASES3(Reg_s17, Reg_d8 , Reg_q4)) \
124 X(Reg_s18, 18, "s18", 0, 1, 0, 0, 0, 1, 0, 0, \ 163 X(Reg_s18, 18, "s18", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
125 ALIASES3(Reg_s18, Reg_d9 , Reg_q4)) \ 164 ALIASES3(Reg_s18, Reg_d9 , Reg_q4)) \
126 X(Reg_s19, 19, "s19", 0, 1, 0, 0, 0, 1, 0, 0, \ 165 X(Reg_s19, 19, "s19", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
127 ALIASES3(Reg_s19, Reg_d9 , Reg_q4)) \ 166 ALIASES3(Reg_s19, Reg_d9 , Reg_q4)) \
128 X(Reg_s20, 20, "s20", 0, 1, 0, 0, 0, 1, 0, 0, \ 167 X(Reg_s20, 20, "s20", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
129 ALIASES3(Reg_s20, Reg_d10, Reg_q5)) \ 168 ALIASES3(Reg_s20, Reg_d10, Reg_q5)) \
130 X(Reg_s21, 21, "s21", 0, 1, 0, 0, 0, 1, 0, 0, \ 169 X(Reg_s21, 21, "s21", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
131 ALIASES3(Reg_s21, Reg_d10, Reg_q5)) \ 170 ALIASES3(Reg_s21, Reg_d10, Reg_q5)) \
132 X(Reg_s22, 22, "s22", 0, 1, 0, 0, 0, 1, 0, 0, \ 171 X(Reg_s22, 22, "s22", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
133 ALIASES3(Reg_s22, Reg_d11, Reg_q5)) \ 172 ALIASES3(Reg_s22, Reg_d11, Reg_q5)) \
134 X(Reg_s23, 23, "s23", 0, 1, 0, 0, 0, 1, 0, 0, \ 173 X(Reg_s23, 23, "s23", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
135 ALIASES3(Reg_s23, Reg_d11, Reg_q5)) \ 174 ALIASES3(Reg_s23, Reg_d11, Reg_q5)) \
136 X(Reg_s24, 24, "s24", 0, 1, 0, 0, 0, 1, 0, 0, \ 175 X(Reg_s24, 24, "s24", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
137 ALIASES3(Reg_s24, Reg_d12, Reg_q6)) \ 176 ALIASES3(Reg_s24, Reg_d12, Reg_q6)) \
138 X(Reg_s25, 25, "s25", 0, 1, 0, 0, 0, 1, 0, 0, \ 177 X(Reg_s25, 25, "s25", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
139 ALIASES3(Reg_s25, Reg_d12, Reg_q6)) \ 178 ALIASES3(Reg_s25, Reg_d12, Reg_q6)) \
140 X(Reg_s26, 26, "s26", 0, 1, 0, 0, 0, 1, 0, 0, \ 179 X(Reg_s26, 26, "s26", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
141 ALIASES3(Reg_s26, Reg_d13, Reg_q6)) \ 180 ALIASES3(Reg_s26, Reg_d13, Reg_q6)) \
142 X(Reg_s27, 27, "s27", 0, 1, 0, 0, 0, 1, 0, 0, \ 181 X(Reg_s27, 27, "s27", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
143 ALIASES3(Reg_s27, Reg_d13, Reg_q6)) \ 182 ALIASES3(Reg_s27, Reg_d13, Reg_q6)) \
144 X(Reg_s28, 28, "s28", 0, 1, 0, 0, 0, 1, 0, 0, \ 183 X(Reg_s28, 28, "s28", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
145 ALIASES3(Reg_s28, Reg_d14, Reg_q7)) \ 184 ALIASES3(Reg_s28, Reg_d14, Reg_q7)) \
146 X(Reg_s29, 29, "s29", 0, 1, 0, 0, 0, 1, 0, 0, \ 185 X(Reg_s29, 29, "s29", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
147 ALIASES3(Reg_s29, Reg_d14, Reg_q7)) \ 186 ALIASES3(Reg_s29, Reg_d14, Reg_q7)) \
148 X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 1, 0, 0, \ 187 X(Reg_s30, 30, "s30", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
149 ALIASES3(Reg_s30, Reg_d15, Reg_q7)) \ 188 ALIASES3(Reg_s30, Reg_d15, Reg_q7)) \
150 X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 1, 0, 0, \ 189 X(Reg_s31, 31, "s31", 0, 1, 0, 0, 0, 0, 1, 0, 0, \
151 ALIASES3(Reg_s31, Reg_d15, Reg_q7)) 190 ALIASES3(Reg_s31, Reg_d15, Reg_q7))
152 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 191 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
153 // isInt, isFP32,isFP64, isVec128, aliases_init) 192 // isInt, isI64Pair, isFP32,isFP64, isVec128, aliases_init)
154 193
155 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch 194 // D registers 0-7 are scratch, 8-15 are preserved, and 16-31 are also scratch
156 // (if supported by the D32 feature vs D16). D registers are defined in reverse 195 // (if supported by the D32 feature vs D16). D registers are defined in reverse
157 // order so that, during register allocation, Subzero will prefer higher D 196 // order so that, during register allocation, Subzero will prefer higher D
158 // registers. In processors supporting the D32 feature this will effectively 197 // registers. In processors supporting the D32 feature this will effectively
159 // cause double allocation to bias towards allocating "high" D registers, which 198 // cause double allocation to bias towards allocating "high" D registers, which
160 // do not alias any S registers. 199 // do not alias any S registers.
161 // 200 //
162 // Regenerate this with the following python script: 201 // Regenerate this with the following python script:
163 // def print_dregs(): 202 // def print_dregs():
164 // for i in xrange(31, 15, -1): 203 // for i in xrange(31, 15, -1):
165 // is_scratch = 1 if (i < 8 or i >= 16) else 0 204 // is_scratch = 1 if (i < 8 or i >= 16) else 0
166 // is_preserved = 1 if (8 <= i and i < 16) else 0 205 // is_preserved = 1 if (8 <= i and i < 16) else 0
167 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' + 206 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
168 // '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, ' + 207 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' +
169 // 'ALIASES(Reg_d{regnum:<2}, Reg_q{regnum_q:<2}) \\').format( 208 // 'ALIASES(Reg_d{regnum:<2}, Reg_q{regnum_q:<2}) \\').format(
170 // regnum=i, regnum_q=i>>1, scratch=is_scratch, 209 // regnum=i, regnum_q=i>>1, scratch=is_scratch,
171 // preserved=is_preserved) 210 // preserved=is_preserved)
172 // for i in xrange(15, -1, -1): 211 // for i in xrange(15, -1, -1):
173 // is_scratch = 1 if (i < 8 or i >= 16) else 0 212 // is_scratch = 1 if (i < 8 or i >= 16) else 0
174 // is_preserved = 1 if (8 <= i and i < 16) else 0 213 // is_preserved = 1 if (8 <= i and i < 16) else 0
175 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' + 214 // print (' X(Reg_d{regnum:<2}, {regnum:<2}, "d{regnum}", ' +
176 // '{scratch}, {preserved}, 0, 0, 0, 0, 1, 0, ' + 215 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, 0, ' +
177 // 'ALIASES(Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' + 216 // 'ALIASES(Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' +
178 // 'Reg_d{regnum:<2}, Reg_q{regnum_q:<2})) \\').format( 217 // 'Reg_d{regnum:<2}, Reg_q{regnum_q:<2})) \\').format(
179 // regnum_s0 = (i<<1), regnum_s1 = (i<<1) + 1, regnum=i, 218 // regnum_s0 = (i<<1), regnum_s1 = (i<<1) + 1, regnum=i,
180 // regnum_q=i>>1, scratch=is_scratch, preserved=is_preserved) 219 // regnum_q=i>>1, scratch=is_scratch, preserved=is_preserved)
181 // 220 //
182 // print_dregs() 221 // print_dregs()
183 // 222 //
184 #define REGARM32_FP64_TABLE \ 223 #define REGARM32_FP64_TABLE \
185 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 224 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
186 isInt, isFP32, isFP64, isVec128, aliases_init */ \ 225 isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init */ \
187 X(Reg_d31, 31, "d31", 1, 0, 0, 0, 0, 0, 1, 0, \ 226 X(Reg_d31, 31, "d31", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
188 ALIASES2(Reg_d31, Reg_q15)) \ 227 ALIASES2(Reg_d31, Reg_q15)) \
189 X(Reg_d30, 30, "d30", 1, 0, 0, 0, 0, 0, 1, 0, \ 228 X(Reg_d30, 30, "d30", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
190 ALIASES2(Reg_d30, Reg_q15)) \ 229 ALIASES2(Reg_d30, Reg_q15)) \
191 X(Reg_d29, 29, "d29", 1, 0, 0, 0, 0, 0, 1, 0, \ 230 X(Reg_d29, 29, "d29", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
192 ALIASES2(Reg_d29, Reg_q14)) \ 231 ALIASES2(Reg_d29, Reg_q14)) \
193 X(Reg_d28, 28, "d28", 1, 0, 0, 0, 0, 0, 1, 0, \ 232 X(Reg_d28, 28, "d28", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
194 ALIASES2(Reg_d28, Reg_q14)) \ 233 ALIASES2(Reg_d28, Reg_q14)) \
195 X(Reg_d27, 27, "d27", 1, 0, 0, 0, 0, 0, 1, 0, \ 234 X(Reg_d27, 27, "d27", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
196 ALIASES2(Reg_d27, Reg_q13)) \ 235 ALIASES2(Reg_d27, Reg_q13)) \
197 X(Reg_d26, 26, "d26", 1, 0, 0, 0, 0, 0, 1, 0, \ 236 X(Reg_d26, 26, "d26", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
198 ALIASES2(Reg_d26, Reg_q13)) \ 237 ALIASES2(Reg_d26, Reg_q13)) \
199 X(Reg_d25, 25, "d25", 1, 0, 0, 0, 0, 0, 1, 0, \ 238 X(Reg_d25, 25, "d25", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
200 ALIASES2(Reg_d25, Reg_q12)) \ 239 ALIASES2(Reg_d25, Reg_q12)) \
201 X(Reg_d24, 24, "d24", 1, 0, 0, 0, 0, 0, 1, 0, \ 240 X(Reg_d24, 24, "d24", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
202 ALIASES2(Reg_d24, Reg_q12)) \ 241 ALIASES2(Reg_d24, Reg_q12)) \
203 X(Reg_d23, 23, "d23", 1, 0, 0, 0, 0, 0, 1, 0, \ 242 X(Reg_d23, 23, "d23", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
204 ALIASES2(Reg_d23, Reg_q11)) \ 243 ALIASES2(Reg_d23, Reg_q11)) \
205 X(Reg_d22, 22, "d22", 1, 0, 0, 0, 0, 0, 1, 0, \ 244 X(Reg_d22, 22, "d22", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
206 ALIASES2(Reg_d22, Reg_q11)) \ 245 ALIASES2(Reg_d22, Reg_q11)) \
207 X(Reg_d21, 21, "d21", 1, 0, 0, 0, 0, 0, 1, 0, \ 246 X(Reg_d21, 21, "d21", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
208 ALIASES2(Reg_d21, Reg_q10)) \ 247 ALIASES2(Reg_d21, Reg_q10)) \
209 X(Reg_d20, 20, "d20", 1, 0, 0, 0, 0, 0, 1, 0, \ 248 X(Reg_d20, 20, "d20", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
210 ALIASES2(Reg_d20, Reg_q10)) \ 249 ALIASES2(Reg_d20, Reg_q10)) \
211 X(Reg_d19, 19, "d19", 1, 0, 0, 0, 0, 0, 1, 0, \ 250 X(Reg_d19, 19, "d19", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
212 ALIASES2(Reg_d19, Reg_q9)) \ 251 ALIASES2(Reg_d19, Reg_q9)) \
213 X(Reg_d18, 18, "d18", 1, 0, 0, 0, 0, 0, 1, 0, \ 252 X(Reg_d18, 18, "d18", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
214 ALIASES2(Reg_d18, Reg_q9)) \ 253 ALIASES2(Reg_d18, Reg_q9)) \
215 X(Reg_d17, 17, "d17", 1, 0, 0, 0, 0, 0, 1, 0, \ 254 X(Reg_d17, 17, "d17", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
216 ALIASES2(Reg_d17, Reg_q8)) \ 255 ALIASES2(Reg_d17, Reg_q8)) \
217 X(Reg_d16, 16, "d16", 1, 0, 0, 0, 0, 0, 1, 0, \ 256 X(Reg_d16, 16, "d16", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
218 ALIASES2(Reg_d16, Reg_q8)) \ 257 ALIASES2(Reg_d16, Reg_q8)) \
219 X(Reg_d15, 15, "d15", 0, 1, 0, 0, 0, 0, 1, 0, \ 258 X(Reg_d15, 15, "d15", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
220 ALIASES4(Reg_s30, Reg_s31, Reg_d15, Reg_q7)) \ 259 ALIASES4(Reg_s30, Reg_s31, Reg_d15, Reg_q7)) \
221 X(Reg_d14, 14, "d14", 0, 1, 0, 0, 0, 0, 1, 0, \ 260 X(Reg_d14, 14, "d14", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
222 ALIASES4(Reg_s28, Reg_s29, Reg_d14, Reg_q7)) \ 261 ALIASES4(Reg_s28, Reg_s29, Reg_d14, Reg_q7)) \
223 X(Reg_d13, 13, "d13", 0, 1, 0, 0, 0, 0, 1, 0, \ 262 X(Reg_d13, 13, "d13", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
224 ALIASES4(Reg_s26, Reg_s27, Reg_d13, Reg_q6)) \ 263 ALIASES4(Reg_s26, Reg_s27, Reg_d13, Reg_q6)) \
225 X(Reg_d12, 12, "d12", 0, 1, 0, 0, 0, 0, 1, 0, \ 264 X(Reg_d12, 12, "d12", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
226 ALIASES4(Reg_s24, Reg_s25, Reg_d12, Reg_q6)) \ 265 ALIASES4(Reg_s24, Reg_s25, Reg_d12, Reg_q6)) \
227 X(Reg_d11, 11, "d11", 0, 1, 0, 0, 0, 0, 1, 0, \ 266 X(Reg_d11, 11, "d11", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
228 ALIASES4(Reg_s22, Reg_s23, Reg_d11, Reg_q5)) \ 267 ALIASES4(Reg_s22, Reg_s23, Reg_d11, Reg_q5)) \
229 X(Reg_d10, 10, "d10", 0, 1, 0, 0, 0, 0, 1, 0, \ 268 X(Reg_d10, 10, "d10", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
230 ALIASES4(Reg_s20, Reg_s21, Reg_d10, Reg_q5)) \ 269 ALIASES4(Reg_s20, Reg_s21, Reg_d10, Reg_q5)) \
231 X(Reg_d9 , 9 , "d9", 0, 1, 0, 0, 0, 0, 1, 0, \ 270 X(Reg_d9 , 9 , "d9", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
232 ALIASES4(Reg_s18, Reg_s19, Reg_d9 , Reg_q4)) \ 271 ALIASES4(Reg_s18, Reg_s19, Reg_d9 , Reg_q4)) \
233 X(Reg_d8 , 8 , "d8", 0, 1, 0, 0, 0, 0, 1, 0, \ 272 X(Reg_d8 , 8 , "d8", 0, 1, 0, 0, 0, 0, 0, 1, 0, \
234 ALIASES4(Reg_s16, Reg_s17, Reg_d8 , Reg_q4)) \ 273 ALIASES4(Reg_s16, Reg_s17, Reg_d8 , Reg_q4)) \
235 X(Reg_d7 , 7 , "d7", 1, 0, 0, 0, 0, 0, 1, 0, \ 274 X(Reg_d7 , 7 , "d7", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
236 ALIASES4(Reg_s14, Reg_s15, Reg_d7 , Reg_q3)) \ 275 ALIASES4(Reg_s14, Reg_s15, Reg_d7 , Reg_q3)) \
237 X(Reg_d6 , 6 , "d6", 1, 0, 0, 0, 0, 0, 1, 0, \ 276 X(Reg_d6 , 6 , "d6", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
238 ALIASES4(Reg_s12, Reg_s13, Reg_d6 , Reg_q3)) \ 277 ALIASES4(Reg_s12, Reg_s13, Reg_d6 , Reg_q3)) \
239 X(Reg_d5 , 5 , "d5", 1, 0, 0, 0, 0, 0, 1, 0, \ 278 X(Reg_d5 , 5 , "d5", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
240 ALIASES4(Reg_s10, Reg_s11, Reg_d5 , Reg_q2)) \ 279 ALIASES4(Reg_s10, Reg_s11, Reg_d5 , Reg_q2)) \
241 X(Reg_d4 , 4 , "d4", 1, 0, 0, 0, 0, 0, 1, 0, \ 280 X(Reg_d4 , 4 , "d4", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
242 ALIASES4(Reg_s8 , Reg_s9 , Reg_d4 , Reg_q2)) \ 281 ALIASES4(Reg_s8 , Reg_s9 , Reg_d4 , Reg_q2)) \
243 X(Reg_d3 , 3 , "d3", 1, 0, 0, 0, 0, 0, 1, 0, \ 282 X(Reg_d3 , 3 , "d3", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
244 ALIASES4(Reg_s6 , Reg_s7 , Reg_d3 , Reg_q1)) \ 283 ALIASES4(Reg_s6 , Reg_s7 , Reg_d3 , Reg_q1)) \
245 X(Reg_d2 , 2 , "d2", 1, 0, 0, 0, 0, 0, 1, 0, \ 284 X(Reg_d2 , 2 , "d2", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
246 ALIASES4(Reg_s4 , Reg_s5 , Reg_d2 , Reg_q1)) \ 285 ALIASES4(Reg_s4 , Reg_s5 , Reg_d2 , Reg_q1)) \
247 X(Reg_d1 , 1 , "d1", 1, 0, 0, 0, 0, 0, 1, 0, \ 286 X(Reg_d1 , 1 , "d1", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
248 ALIASES4(Reg_s2 , Reg_s3 , Reg_d1 , Reg_q0)) \ 287 ALIASES4(Reg_s2 , Reg_s3 , Reg_d1 , Reg_q0)) \
249 X(Reg_d0 , 0 , "d0", 1, 0, 0, 0, 0, 0, 1, 0, \ 288 X(Reg_d0 , 0 , "d0", 1, 0, 0, 0, 0, 0, 0, 1, 0, \
250 ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0)) 289 ALIASES4(Reg_s0 , Reg_s1 , Reg_d0 , Reg_q0))
251 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 290 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
252 // isInt, isFP32, isFP64, isVec128, aliases_init) 291 // isInt, isI64Pair, isFP32, isFP64, isVec128, aliases_init)
253 292
254 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch 293 // Q registers 0-3 are scratch, 4-7 are preserved, and 8-15 are also scratch
255 // (if supported by the D32 feature). Q registers are defined in reverse order 294 // (if supported by the D32 feature). Q registers are defined in reverse order
256 // for the same reason as D registers. 295 // for the same reason as D registers.
257 // 296 //
258 // Regenerate this with the following python script: 297 // Regenerate this with the following python script:
259 // def print_qregs(): 298 // def print_qregs():
260 // for i in xrange(15, 7, -1): 299 // for i in xrange(15, 7, -1):
261 // is_scratch = 1 if (i < 4 or i >= 8) else 0 300 // is_scratch = 1 if (i < 4 or i >= 8) else 0
262 // is_preserved = 1 if (4 <= i and i < 8) else 0 301 // is_preserved = 1 if (4 <= i and i < 8) else 0
263 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' + 302 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
264 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, ALIASES(' + 303 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, ALIASES(' +
265 // 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' + 304 // 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' +
266 // 'Reg_q{regnum:<2})) \\').format( 305 // 'Reg_q{regnum:<2})) \\').format(
267 // regnum_d0=(i<<1), regnum_d1=(i<<1)+1, regnum=i, 306 // regnum_d0=(i<<1), regnum_d1=(i<<1)+1, regnum=i,
268 // scratch=is_scratch, preserved=is_preserved) 307 // scratch=is_scratch, preserved=is_preserved)
269 // for i in xrange(7, -1, -1): 308 // for i in xrange(7, -1, -1):
270 // is_scratch = 1 if (i < 4 or i >= 8) else 0 309 // is_scratch = 1 if (i < 4 or i >= 8) else 0
271 // is_preserved = 1 if (4 <= i and i < 8) else 0 310 // is_preserved = 1 if (4 <= i and i < 8) else 0
272 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' + 311 // print (' X(Reg_q{regnum:<2}, {regnum:<2}, "q{regnum}", ' +
273 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 1, ALIASES(' + 312 // '{scratch}, {preserved}, 0, 0, 0, 0, 0, 0, 1, ALIASES(' +
274 // 'Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' + 313 // 'Reg_s{regnum_s0:<2}, Reg_s{regnum_s1:<2}, ' +
275 // 'Reg_s{regnum_s2:<2}, Reg_s{regnum_s3:<2}, ' + 314 // 'Reg_s{regnum_s2:<2}, Reg_s{regnum_s3:<2}, ' +
276 // 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' + 315 // 'Reg_d{regnum_d0:<2}, Reg_d{regnum_d1:<2}, ' +
277 // 'Reg_q{regnum:<2})) \\').format( 316 // 'Reg_q{regnum:<2})) \\').format(
278 // regnum_s0=(i<<2), regnum_s1=(i<<2)+1, regnum_s2=(i<<2)+2, 317 // regnum_s0=(i<<2), regnum_s1=(i<<2)+1, regnum_s2=(i<<2)+2,
279 // regnum_s3=(i<<2)+3, regnum_d0=(i<<1), regnum_d1=(i<<1)+1, 318 // regnum_s3=(i<<2)+3, regnum_d0=(i<<1), regnum_d1=(i<<1)+1,
280 // regnum=i, scratch=is_scratch, preserved=is_preserved) 319 // regnum=i, scratch=is_scratch, preserved=is_preserved)
281 // 320 //
282 // print_qregs() 321 // print_qregs()
283 // 322 //
284 #define REGARM32_VEC128_TABLE \ 323 #define REGARM32_VEC128_TABLE \
285 /* val, encode, name, scratch, preserved, stackptr, frameptr, \ 324 /* val, encode, name, scratch, preserved, stackptr, frameptr, \
286 isInt, isFP32, isFP64, isVec128, alias_init */ \ 325 isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init */ \
287 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 1, \ 326 X(Reg_q15, 15, "q15", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
288 ALIASES3(Reg_d30, Reg_d31, Reg_q15)) \ 327 ALIASES3(Reg_d30, Reg_d31, Reg_q15)) \
289 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 1, \ 328 X(Reg_q14, 14, "q14", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
290 ALIASES3(Reg_d28, Reg_d29, Reg_q14)) \ 329 ALIASES3(Reg_d28, Reg_d29, Reg_q14)) \
291 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 1, \ 330 X(Reg_q13, 13, "q13", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
292 ALIASES3(Reg_d26, Reg_d27, Reg_q13)) \ 331 ALIASES3(Reg_d26, Reg_d27, Reg_q13)) \
293 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 1, \ 332 X(Reg_q12, 12, "q12", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
294 ALIASES3(Reg_d24, Reg_d25, Reg_q12)) \ 333 ALIASES3(Reg_d24, Reg_d25, Reg_q12)) \
295 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 1, \ 334 X(Reg_q11, 11, "q11", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
296 ALIASES3(Reg_d22, Reg_d23, Reg_q11)) \ 335 ALIASES3(Reg_d22, Reg_d23, Reg_q11)) \
297 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 1, \ 336 X(Reg_q10, 10, "q10", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
298 ALIASES3(Reg_d20, Reg_d21, Reg_q10)) \ 337 ALIASES3(Reg_d20, Reg_d21, Reg_q10)) \
299 X(Reg_q9 , 9 , "q9", 1, 0, 0, 0, 0, 0, 0, 1, \ 338 X(Reg_q9 , 9 , "q9", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
300 ALIASES3(Reg_d18, Reg_d19, Reg_q9)) \ 339 ALIASES3(Reg_d18, Reg_d19, Reg_q9)) \
301 X(Reg_q8 , 8 , "q8", 1, 0, 0, 0, 0, 0, 0, 1, \ 340 X(Reg_q8 , 8 , "q8", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
302 ALIASES3(Reg_d16, Reg_d17, Reg_q8)) \ 341 ALIASES3(Reg_d16, Reg_d17, Reg_q8)) \
303 X(Reg_q7 , 7 , "q7", 0, 1, 0, 0, 0, 0, 0, 1, \ 342 X(Reg_q7 , 7 , "q7", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
304 ALIASES7(Reg_s28, Reg_s29, Reg_s30, Reg_s31, Reg_d14, Reg_d15, Reg_q7)) \ 343 ALIASES7(Reg_s28, Reg_s29, Reg_s30, Reg_s31, Reg_d14, Reg_d15, Reg_q7)) \
305 X(Reg_q6 , 6 , "q6", 0, 1, 0, 0, 0, 0, 0, 1, \ 344 X(Reg_q6 , 6 , "q6", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
306 ALIASES7(Reg_s24, Reg_s25, Reg_s26, Reg_s27, Reg_d12, Reg_d13, Reg_q6)) \ 345 ALIASES7(Reg_s24, Reg_s25, Reg_s26, Reg_s27, Reg_d12, Reg_d13, Reg_q6)) \
307 X(Reg_q5 , 5 , "q5", 0, 1, 0, 0, 0, 0, 0, 1, \ 346 X(Reg_q5 , 5 , "q5", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
308 ALIASES7(Reg_s20, Reg_s21, Reg_s22, Reg_s23, Reg_d10, Reg_d11, Reg_q5)) \ 347 ALIASES7(Reg_s20, Reg_s21, Reg_s22, Reg_s23, Reg_d10, Reg_d11, Reg_q5)) \
309 X(Reg_q4 , 4 , "q4", 0, 1, 0, 0, 0, 0, 0, 1, \ 348 X(Reg_q4 , 4 , "q4", 0, 1, 0, 0, 0, 0, 0, 0, 1, \
310 ALIASES7(Reg_s16, Reg_s17, Reg_s18, Reg_s19, Reg_d8 , Reg_d9 , Reg_q4)) \ 349 ALIASES7(Reg_s16, Reg_s17, Reg_s18, Reg_s19, Reg_d8 , Reg_d9 , Reg_q4)) \
311 X(Reg_q3 , 3 , "q3", 1, 0, 0, 0, 0, 0, 0, 1, \ 350 X(Reg_q3 , 3 , "q3", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
312 ALIASES7(Reg_s12, Reg_s13, Reg_s14, Reg_s15, Reg_d6 , Reg_d7 , Reg_q3)) \ 351 ALIASES7(Reg_s12, Reg_s13, Reg_s14, Reg_s15, Reg_d6 , Reg_d7 , Reg_q3)) \
313 X(Reg_q2 , 2 , "q2", 1, 0, 0, 0, 0, 0, 0, 1, \ 352 X(Reg_q2 , 2 , "q2", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
314 ALIASES7(Reg_s8 , Reg_s9 , Reg_s10, Reg_s11, Reg_d4 , Reg_d5 , Reg_q2)) \ 353 ALIASES7(Reg_s8 , Reg_s9 , Reg_s10, Reg_s11, Reg_d4 , Reg_d5 , Reg_q2)) \
315 X(Reg_q1 , 1 , "q1", 1, 0, 0, 0, 0, 0, 0, 1, \ 354 X(Reg_q1 , 1 , "q1", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
316 ALIASES7(Reg_s4 , Reg_s5 , Reg_s6 , Reg_s7 , Reg_d2 , Reg_d3 , Reg_q1)) \ 355 ALIASES7(Reg_s4 , Reg_s5 , Reg_s6 , Reg_s7 , Reg_d2 , Reg_d3 , Reg_q1)) \
317 X(Reg_q0 , 0 , "q0", 1, 0, 0, 0, 0, 0, 0, 1, \ 356 X(Reg_q0 , 0 , "q0", 1, 0, 0, 0, 0, 0, 0, 0, 1, \
318 ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0)) 357 ALIASES7(Reg_s0 , Reg_s1 , Reg_s2 , Reg_s3 , Reg_d0 , Reg_d1 , Reg_q0))
319 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 358 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
320 // isInt, isFP32, isFP64, isVec128, alias_init) 359 // isInt, isI64Pair, isFP32, isFP64, isVec128, alias_init)
321 #undef ALIASES 360 #undef ALIASES
322 361
323 // We also provide a combined table, so that there is a namespace where all of 362 // We also provide a combined table, so that there is a namespace where all of
324 // the registers are considered and have distinct numberings. This is in 363 // the registers are considered and have distinct numberings. This is in
325 // contrast to the above, where the "encode" is based on how the register 364 // contrast to the above, where the "encode" is based on how the register
326 // numbers will be encoded in binaries and values can overlap. 365 // numbers will be encoded in binaries and values can overlap.
327 #define REGARM32_TABLE \ 366 #define REGARM32_TABLE \
328 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \ 367 /* val, encode, name, scratch, preserved, stackptr, frameptr, isInt, \
329 isFP32, isFP64, isVec128, alias_init */ \ 368 isFP32, isFP64, isVec128, alias_init */ \
330 REGARM32_GPR_TABLE \ 369 REGARM32_GPR_TABLE \
370 REGARM32_I64PAIR_TABLE \
331 REGARM32_FP32_TABLE \ 371 REGARM32_FP32_TABLE \
332 REGARM32_FP64_TABLE \ 372 REGARM32_FP64_TABLE \
333 REGARM32_VEC128_TABLE 373 REGARM32_VEC128_TABLE
334 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr, 374 //#define X(val, encode, name, scratch, preserved, stackptr, frameptr,
335 // isInt, isFP32, isFP64, isVec128, alias_init) 375 // isInt, isFP32, isFP64, isVec128, alias_init)
336 376
337 #define REGARM32_TABLE_BOUNDS \ 377 #define REGARM32_TABLE_BOUNDS \
338 /* val, init */ \ 378 /* val, init */ \
339 X(Reg_GPR_First, = Reg_r0) \ 379 X(Reg_GPR_First, = Reg_r0) \
340 X(Reg_GPR_Last, = Reg_pc) \ 380 X(Reg_GPR_Last, = Reg_pc) \
381 X(Reg_I64PAIR_First, = Reg_r0r1) \
382 X(Reg_I64PAIR_Last, = Reg_r10fp) \
341 X(Reg_SREG_First, = Reg_s0) \ 383 X(Reg_SREG_First, = Reg_s0) \
342 X(Reg_SREG_Last, = Reg_s31) \ 384 X(Reg_SREG_Last, = Reg_s31) \
343 X(Reg_DREG_First, = Reg_d0) \ 385 X(Reg_DREG_First, = Reg_d0) \
344 X(Reg_DREG_Last, = Reg_d31) \ 386 X(Reg_DREG_Last, = Reg_d31) \
345 X(Reg_QREG_First, = Reg_q0) \ 387 X(Reg_QREG_First, = Reg_q0) \
346 X(Reg_QREG_Last, = Reg_q15) 388 X(Reg_QREG_Last, = Reg_q15)
347 // define X(val, init) 389 // define X(val, init)
348 390
349 // Load/Store instruction width suffixes and FP/Vector element size suffixes 391 // Load/Store instruction width suffixes and FP/Vector element size suffixes
350 // the # of offset bits allowed as part of an addressing mode (for sign or zero 392 // the # of offset bits allowed as part of an addressing mode (for sign or zero
351 // extending load/stores). 393 // extending load/stores).
352 #define ICETYPEARM32_TABLE \ 394 #define ICETYPEARM32_TABLE \
353 /* tag, element type, int_width, vec_width, addr bits sext, zext, \ 395 /* tag, element type, int_width, vec_width, addr bits sext, zext, \
354 reg-reg addr allowed */ \ 396 reg-reg addr allowed */ \
355 X(IceType_void, IceType_void, "" , "" , 0 , 0 , 0) \ 397 X(IceType_void, IceType_void, "" , "" , 0 , 0 , 0) \
356 X(IceType_i1, IceType_void, "b", "" , 8 , 12, 1) \ 398 X(IceType_i1, IceType_void, "b", "" , 8 , 12, 1) \
357 X(IceType_i8, IceType_void, "b", "" , 8 , 12, 1) \ 399 X(IceType_i8, IceType_void, "b", "" , 8 , 12, 1) \
358 X(IceType_i16, IceType_void, "h", "" , 8 , 8 , 1) \ 400 X(IceType_i16, IceType_void, "h", "" , 8 , 8 , 1) \
359 X(IceType_i32, IceType_void, "" , "" , 12, 12, 1) \ 401 X(IceType_i32, IceType_void, "" , "" , 12, 12, 1) \
360 X(IceType_i64, IceType_void, "d", "" , 8 , 8 , 1) \ 402 X(IceType_i64, IceType_void, "d", "" , 0 , 0 , 0) \
361 X(IceType_f32, IceType_void, "" , ".f32", 8, 8 , 0) \ 403 X(IceType_f32, IceType_void, "" , ".f32", 8, 8 , 0) \
362 X(IceType_f64, IceType_void, "" , ".f64", 8, 8 , 0) \ 404 X(IceType_f64, IceType_void, "" , ".f64", 8, 8 , 0) \
363 X(IceType_v4i1, IceType_i32 , "" , ".i32", 0 , 0 , 1) \ 405 X(IceType_v4i1, IceType_i32 , "" , ".i32", 0 , 0 , 1) \
364 X(IceType_v8i1, IceType_i16 , "" , ".i16", 0 , 0 , 1) \ 406 X(IceType_v8i1, IceType_i16 , "" , ".i16", 0 , 0 , 1) \
365 X(IceType_v16i1, IceType_i8 , "" , ".i8" , 0 , 0 , 1) \ 407 X(IceType_v16i1, IceType_i8 , "" , ".i8" , 0 , 0 , 1) \
366 X(IceType_v16i8, IceType_i8 , "" , ".i8" , 0 , 0 , 1) \ 408 X(IceType_v16i8, IceType_i8 , "" , ".i8" , 0 , 0 , 1) \
367 X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1) \ 409 X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1) \
368 X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1) \ 410 X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1) \
369 X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1) 411 X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1)
370 //#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr) 412 //#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr)
371 413
372 // Shifter types for Data-processing operands as defined in section A5.1.2. 414 // Shifter types for Data-processing operands as defined in section A5.1.2.
373 #define ICEINSTARM32SHIFT_TABLE \ 415 #define ICEINSTARM32SHIFT_TABLE \
374 /* enum value, emit */ \ 416 /* enum value, emit */ \
375 X(LSL, "lsl") \ 417 X(LSL, "lsl") \
376 X(LSR, "lsr") \ 418 X(LSR, "lsr") \
377 X(ASR, "asr") \ 419 X(ASR, "asr") \
378 X(ROR, "ror") \ 420 X(ROR, "ror") \
(...skipping 14 matching lines...) Expand all
393 X(VS, 6 , VC, "vs") /* overflow (float unordered) */ \ 435 X(VS, 6 , VC, "vs") /* overflow (float unordered) */ \
394 X(VC, 7 , VS, "vc") /* no overflow (float not unordered) */ \ 436 X(VC, 7 , VS, "vc") /* no overflow (float not unordered) */ \
395 X(HI, 8 , LS, "hi") /* unsigned higher */ \ 437 X(HI, 8 , LS, "hi") /* unsigned higher */ \
396 X(LS, 9 , HI, "ls") /* unsigned lower or same */ \ 438 X(LS, 9 , HI, "ls") /* unsigned lower or same */ \
397 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ 439 X(GE, 10, LT, "ge") /* signed greater than or equal */ \
398 X(LT, 11, GE, "lt") /* signed less than */ \ 440 X(LT, 11, GE, "lt") /* signed less than */ \
399 X(GT, 12, LE, "gt") /* signed greater than */ \ 441 X(GT, 12, LE, "gt") /* signed greater than */ \
400 X(LE, 13, GT, "le") /* signed less than or equal */ \ 442 X(LE, 13, GT, "le") /* signed less than or equal */ \
401 X(AL, 14, kNone, "") /* always (unconditional) */ \ 443 X(AL, 14, kNone, "") /* always (unconditional) */ \
402 X(kNone, 15, kNone, "??") /* special condition / none */ 444 X(kNone, 15, kNone, "??") /* special condition / none */
403 //#define(tag, encode, opp, emit) 445 //#define X(tag, encode, opp, emit)
404 446
405 #endif // SUBZERO_SRC_ICEINSTARM32_DEF 447 #endif // SUBZERO_SRC_ICEINSTARM32_DEF
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