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1 // Copyright (c) 1994-2006 Sun Microsystems Inc. | 1 // Copyright (c) 1994-2006 Sun Microsystems Inc. |
2 // All Rights Reserved. | 2 // All Rights Reserved. |
3 // | 3 // |
4 // Redistribution and use in source and binary forms, with or without | 4 // Redistribution and use in source and binary forms, with or without |
5 // modification, are permitted provided that the following conditions are | 5 // modification, are permitted provided that the following conditions are |
6 // met: | 6 // met: |
7 // | 7 // |
8 // - Redistributions of source code must retain the above copyright notice, | 8 // - Redistributions of source code must retain the above copyright notice, |
9 // this list of conditions and the following disclaimer. | 9 // this list of conditions and the following disclaimer. |
10 // | 10 // |
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57 // generation even when generating snapshots. This won't work for cross | 57 // generation even when generating snapshots. This won't work for cross |
58 // compilation. | 58 // compilation. |
59 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0 | 59 #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0 |
60 answer |= 1u << FPU; | 60 answer |= 1u << FPU; |
61 #endif | 61 #endif |
62 | 62 |
63 return answer; | 63 return answer; |
64 } | 64 } |
65 | 65 |
66 | 66 |
| 67 const char* DoubleRegister::AllocationIndexToString(int index) { |
| 68 DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters); |
| 69 const char* const names[] = { |
| 70 "f0", |
| 71 "f2", |
| 72 "f4", |
| 73 "f6", |
| 74 "f8", |
| 75 "f10", |
| 76 "f12", |
| 77 "f14", |
| 78 "f16", |
| 79 "f18", |
| 80 "f20", |
| 81 "f22", |
| 82 "f24", |
| 83 "f26" |
| 84 }; |
| 85 return names[index]; |
| 86 } |
| 87 |
| 88 |
67 void CpuFeatures::ProbeImpl(bool cross_compile) { | 89 void CpuFeatures::ProbeImpl(bool cross_compile) { |
68 supported_ |= CpuFeaturesImpliedByCompiler(); | 90 supported_ |= CpuFeaturesImpliedByCompiler(); |
69 | 91 |
70 // Only use statically determined features for cross compile (snapshot). | 92 // Only use statically determined features for cross compile (snapshot). |
71 if (cross_compile) return; | 93 if (cross_compile) return; |
72 | 94 |
73 // If the compiler is allowed to use fpu then we can use fpu too in our | 95 // If the compiler is allowed to use fpu then we can use fpu too in our |
74 // code generation. | 96 // code generation. |
75 #ifndef __mips__ | 97 #ifndef __mips__ |
76 // For the simulator build, use FPU. | 98 // For the simulator build, use FPU. |
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200 offset_ = unit * multiplier + offset_addend; | 222 offset_ = unit * multiplier + offset_addend; |
201 } | 223 } |
202 | 224 |
203 | 225 |
204 // ----------------------------------------------------------------------------- | 226 // ----------------------------------------------------------------------------- |
205 // Specific instructions, constants, and masks. | 227 // Specific instructions, constants, and masks. |
206 | 228 |
207 static const int kNegOffset = 0x00008000; | 229 static const int kNegOffset = 0x00008000; |
208 // daddiu(sp, sp, 8) aka Pop() operation or part of Pop(r) | 230 // daddiu(sp, sp, 8) aka Pop() operation or part of Pop(r) |
209 // operations as post-increment of sp. | 231 // operations as post-increment of sp. |
210 const Instr kPopInstruction = DADDIU | (Register::kCode_sp << kRsShift) | | 232 const Instr kPopInstruction = DADDIU | (kRegister_sp_Code << kRsShift) |
211 (Register::kCode_sp << kRtShift) | | 233 | (kRegister_sp_Code << kRtShift) |
212 (kPointerSize & kImm16Mask); // NOLINT | 234 | (kPointerSize & kImm16Mask); // NOLINT |
213 // daddiu(sp, sp, -8) part of Push(r) operation as pre-decrement of sp. | 235 // daddiu(sp, sp, -8) part of Push(r) operation as pre-decrement of sp. |
214 const Instr kPushInstruction = DADDIU | (Register::kCode_sp << kRsShift) | | 236 const Instr kPushInstruction = DADDIU | (kRegister_sp_Code << kRsShift) |
215 (Register::kCode_sp << kRtShift) | | 237 | (kRegister_sp_Code << kRtShift) |
216 (-kPointerSize & kImm16Mask); // NOLINT | 238 | (-kPointerSize & kImm16Mask); // NOLINT |
217 // sd(r, MemOperand(sp, 0)) | 239 // sd(r, MemOperand(sp, 0)) |
218 const Instr kPushRegPattern = | 240 const Instr kPushRegPattern = SD | (kRegister_sp_Code << kRsShift) |
219 SD | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask); // NOLINT | 241 | (0 & kImm16Mask); // NOLINT |
220 // ld(r, MemOperand(sp, 0)) | 242 // ld(r, MemOperand(sp, 0)) |
221 const Instr kPopRegPattern = | 243 const Instr kPopRegPattern = LD | (kRegister_sp_Code << kRsShift) |
222 LD | (Register::kCode_sp << kRsShift) | (0 & kImm16Mask); // NOLINT | 244 | (0 & kImm16Mask); // NOLINT |
223 | 245 |
224 const Instr kLwRegFpOffsetPattern = | 246 const Instr kLwRegFpOffsetPattern = LW | (kRegister_fp_Code << kRsShift) |
225 LW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT | 247 | (0 & kImm16Mask); // NOLINT |
226 | 248 |
227 const Instr kSwRegFpOffsetPattern = | 249 const Instr kSwRegFpOffsetPattern = SW | (kRegister_fp_Code << kRsShift) |
228 SW | (Register::kCode_fp << kRsShift) | (0 & kImm16Mask); // NOLINT | 250 | (0 & kImm16Mask); // NOLINT |
229 | 251 |
230 const Instr kLwRegFpNegOffsetPattern = LW | (Register::kCode_fp << kRsShift) | | 252 const Instr kLwRegFpNegOffsetPattern = LW | (kRegister_fp_Code << kRsShift) |
231 (kNegOffset & kImm16Mask); // NOLINT | 253 | (kNegOffset & kImm16Mask); // NOLINT |
232 | 254 |
233 const Instr kSwRegFpNegOffsetPattern = SW | (Register::kCode_fp << kRsShift) | | 255 const Instr kSwRegFpNegOffsetPattern = SW | (kRegister_fp_Code << kRsShift) |
234 (kNegOffset & kImm16Mask); // NOLINT | 256 | (kNegOffset & kImm16Mask); // NOLINT |
235 // A mask for the Rt register for push, pop, lw, sw instructions. | 257 // A mask for the Rt register for push, pop, lw, sw instructions. |
236 const Instr kRtMask = kRtFieldMask; | 258 const Instr kRtMask = kRtFieldMask; |
237 const Instr kLwSwInstrTypeMask = 0xffe00000; | 259 const Instr kLwSwInstrTypeMask = 0xffe00000; |
238 const Instr kLwSwInstrArgumentMask = ~kLwSwInstrTypeMask; | 260 const Instr kLwSwInstrArgumentMask = ~kLwSwInstrTypeMask; |
239 const Instr kLwSwOffsetMask = kImm16Mask; | 261 const Instr kLwSwOffsetMask = kImm16Mask; |
240 | 262 |
241 | 263 |
242 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size) | 264 Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size) |
243 : AssemblerBase(isolate, buffer, buffer_size), | 265 : AssemblerBase(isolate, buffer, buffer_size), |
244 recorded_ast_id_(TypeFeedbackId::None()), | 266 recorded_ast_id_(TypeFeedbackId::None()), |
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285 | 307 |
286 void Assembler::CodeTargetAlign() { | 308 void Assembler::CodeTargetAlign() { |
287 // No advantage to aligning branch/call targets to more than | 309 // No advantage to aligning branch/call targets to more than |
288 // single instruction, that I am aware of. | 310 // single instruction, that I am aware of. |
289 Align(4); | 311 Align(4); |
290 } | 312 } |
291 | 313 |
292 | 314 |
293 Register Assembler::GetRtReg(Instr instr) { | 315 Register Assembler::GetRtReg(Instr instr) { |
294 Register rt; | 316 Register rt; |
295 rt.reg_code = (instr & kRtFieldMask) >> kRtShift; | 317 rt.code_ = (instr & kRtFieldMask) >> kRtShift; |
296 return rt; | 318 return rt; |
297 } | 319 } |
298 | 320 |
299 | 321 |
300 Register Assembler::GetRsReg(Instr instr) { | 322 Register Assembler::GetRsReg(Instr instr) { |
301 Register rs; | 323 Register rs; |
302 rs.reg_code = (instr & kRsFieldMask) >> kRsShift; | 324 rs.code_ = (instr & kRsFieldMask) >> kRsShift; |
303 return rs; | 325 return rs; |
304 } | 326 } |
305 | 327 |
306 | 328 |
307 Register Assembler::GetRdReg(Instr instr) { | 329 Register Assembler::GetRdReg(Instr instr) { |
308 Register rd; | 330 Register rd; |
309 rd.reg_code = (instr & kRdFieldMask) >> kRdShift; | 331 rd.code_ = (instr & kRdFieldMask) >> kRdShift; |
310 return rd; | 332 return rd; |
311 } | 333 } |
312 | 334 |
313 | 335 |
314 uint32_t Assembler::GetRt(Instr instr) { | 336 uint32_t Assembler::GetRt(Instr instr) { |
315 return (instr & kRtFieldMask) >> kRtShift; | 337 return (instr & kRtFieldMask) >> kRtShift; |
316 } | 338 } |
317 | 339 |
318 | 340 |
319 uint32_t Assembler::GetRtField(Instr instr) { | 341 uint32_t Assembler::GetRtField(Instr instr) { |
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2182 } | 2204 } |
2183 | 2205 |
2184 | 2206 |
2185 void Assembler::movn(Register rd, Register rs, Register rt) { | 2207 void Assembler::movn(Register rd, Register rs, Register rt) { |
2186 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN); | 2208 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN); |
2187 } | 2209 } |
2188 | 2210 |
2189 | 2211 |
2190 void Assembler::movt(Register rd, Register rs, uint16_t cc) { | 2212 void Assembler::movt(Register rd, Register rs, uint16_t cc) { |
2191 Register rt; | 2213 Register rt; |
2192 rt.reg_code = (cc & 0x0007) << 2 | 1; | 2214 rt.code_ = (cc & 0x0007) << 2 | 1; |
2193 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); | 2215 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); |
2194 } | 2216 } |
2195 | 2217 |
2196 | 2218 |
2197 void Assembler::movf(Register rd, Register rs, uint16_t cc) { | 2219 void Assembler::movf(Register rd, Register rs, uint16_t cc) { |
2198 Register rt; | 2220 Register rt; |
2199 rt.reg_code = (cc & 0x0007) << 2 | 0; | 2221 rt.code_ = (cc & 0x0007) << 2 | 0; |
2200 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); | 2222 GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); |
2201 } | 2223 } |
2202 | 2224 |
2203 | 2225 |
2204 void Assembler::min_s(FPURegister fd, FPURegister fs, FPURegister ft) { | 2226 void Assembler::min_s(FPURegister fd, FPURegister fs, FPURegister ft) { |
2205 min(S, fd, fs, ft); | 2227 min(S, fd, fs, ft); |
2206 } | 2228 } |
2207 | 2229 |
2208 | 2230 |
2209 void Assembler::min_d(FPURegister fd, FPURegister fs, FPURegister ft) { | 2231 void Assembler::min_d(FPURegister fd, FPURegister fs, FPURegister ft) { |
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2491 | 2513 |
2492 void Assembler::movz_d(FPURegister fd, FPURegister fs, Register rt) { | 2514 void Assembler::movz_d(FPURegister fd, FPURegister fs, Register rt) { |
2493 DCHECK(kArchVariant == kMips64r2); | 2515 DCHECK(kArchVariant == kMips64r2); |
2494 GenInstrRegister(COP1, D, rt, fs, fd, MOVZ_C); | 2516 GenInstrRegister(COP1, D, rt, fs, fd, MOVZ_C); |
2495 } | 2517 } |
2496 | 2518 |
2497 | 2519 |
2498 void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) { | 2520 void Assembler::movt_s(FPURegister fd, FPURegister fs, uint16_t cc) { |
2499 DCHECK(kArchVariant == kMips64r2); | 2521 DCHECK(kArchVariant == kMips64r2); |
2500 FPURegister ft; | 2522 FPURegister ft; |
2501 ft.reg_code = (cc & 0x0007) << 2 | 1; | 2523 ft.code_ = (cc & 0x0007) << 2 | 1; |
2502 GenInstrRegister(COP1, S, ft, fs, fd, MOVF); | 2524 GenInstrRegister(COP1, S, ft, fs, fd, MOVF); |
2503 } | 2525 } |
2504 | 2526 |
2505 | 2527 |
2506 void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) { | 2528 void Assembler::movt_d(FPURegister fd, FPURegister fs, uint16_t cc) { |
2507 DCHECK(kArchVariant == kMips64r2); | 2529 DCHECK(kArchVariant == kMips64r2); |
2508 FPURegister ft; | 2530 FPURegister ft; |
2509 ft.reg_code = (cc & 0x0007) << 2 | 1; | 2531 ft.code_ = (cc & 0x0007) << 2 | 1; |
2510 GenInstrRegister(COP1, D, ft, fs, fd, MOVF); | 2532 GenInstrRegister(COP1, D, ft, fs, fd, MOVF); |
2511 } | 2533 } |
2512 | 2534 |
2513 | 2535 |
2514 void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) { | 2536 void Assembler::movf_s(FPURegister fd, FPURegister fs, uint16_t cc) { |
2515 DCHECK(kArchVariant == kMips64r2); | 2537 DCHECK(kArchVariant == kMips64r2); |
2516 FPURegister ft; | 2538 FPURegister ft; |
2517 ft.reg_code = (cc & 0x0007) << 2 | 0; | 2539 ft.code_ = (cc & 0x0007) << 2 | 0; |
2518 GenInstrRegister(COP1, S, ft, fs, fd, MOVF); | 2540 GenInstrRegister(COP1, S, ft, fs, fd, MOVF); |
2519 } | 2541 } |
2520 | 2542 |
2521 | 2543 |
2522 void Assembler::movf_d(FPURegister fd, FPURegister fs, uint16_t cc) { | 2544 void Assembler::movf_d(FPURegister fd, FPURegister fs, uint16_t cc) { |
2523 DCHECK(kArchVariant == kMips64r2); | 2545 DCHECK(kArchVariant == kMips64r2); |
2524 FPURegister ft; | 2546 FPURegister ft; |
2525 ft.reg_code = (cc & 0x0007) << 2 | 0; | 2547 ft.code_ = (cc & 0x0007) << 2 | 0; |
2526 GenInstrRegister(COP1, D, ft, fs, fd, MOVF); | 2548 GenInstrRegister(COP1, D, ft, fs, fd, MOVF); |
2527 } | 2549 } |
2528 | 2550 |
2529 | 2551 |
2530 void Assembler::movn_s(FPURegister fd, FPURegister fs, Register rt) { | 2552 void Assembler::movn_s(FPURegister fd, FPURegister fs, Register rt) { |
2531 DCHECK(kArchVariant == kMips64r2); | 2553 DCHECK(kArchVariant == kMips64r2); |
2532 GenInstrRegister(COP1, S, rt, fs, fd, MOVN_C); | 2554 GenInstrRegister(COP1, S, rt, fs, fd, MOVN_C); |
2533 } | 2555 } |
2534 | 2556 |
2535 | 2557 |
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3254 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { | 3276 if (icache_flush_mode != SKIP_ICACHE_FLUSH) { |
3255 CpuFeatures::FlushICache(pc, 4 * Assembler::kInstrSize); | 3277 CpuFeatures::FlushICache(pc, 4 * Assembler::kInstrSize); |
3256 } | 3278 } |
3257 } | 3279 } |
3258 | 3280 |
3259 | 3281 |
3260 } // namespace internal | 3282 } // namespace internal |
3261 } // namespace v8 | 3283 } // namespace v8 |
3262 | 3284 |
3263 #endif // V8_TARGET_ARCH_MIPS64 | 3285 #endif // V8_TARGET_ARCH_MIPS64 |
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