Fix bug in ParallelMoveResolver::EmitSwap: implement swaps of FPU spill slots.

runtime/vm/flow_graph_compiler_arm.cc

 // Copyright (c) 2013, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #include "vm/globals.h"  // Needed here to get TARGET_ARCH_ARM.
 #if defined(TARGET_ARCH_ARM)
 
 #include "vm/flow_graph_compiler.h"
 
 #include "lib/error.h"
@@ skipping 1128 matching lines @@
       MoveMemoryToMemory(destination.ToStackSlotAddress(),
                          source.ToStackSlotAddress());
     }
   } else if (source.IsFpuRegister()) {
     if (destination.IsFpuRegister()) {
       __ vmovd(destination.fpu_reg(), source.fpu_reg());
     } else {
       if (destination.IsDoubleStackSlot()) {
         __ vstrd(source.fpu_reg(), destination.ToStackSlotAddress());
       } else {
-        ASSERT(destination.IsFloat32x4StackSlot() ||
-               destination.IsUint32x4StackSlot());
+        ASSERT(destination.IsQuadStackSlot());
         UNIMPLEMENTED();
       }
     }
   } else if (source.IsDoubleStackSlot()) {
     if (destination.IsFpuRegister()) {
       __ vldrd(destination.fpu_reg(), source.ToStackSlotAddress());
     } else {
       ASSERT(destination.IsDoubleStackSlot());
       __ vldrd(FpuTMP, source.ToStackSlotAddress());
       __ vstrd(FpuTMP, destination.ToStackSlotAddress());
     }
-  } else if (source.IsFloat32x4StackSlot() || source.IsUint32x4StackSlot()) {
+  } else if (source.IsQuadStackSlot()) {
     UNIMPLEMENTED();
   } else {
     ASSERT(source.IsConstant());
     if (destination.IsRegister()) {
       const Object& constant = source.constant();
       __ LoadObject(destination.reg(), constant);
     } else {
       ASSERT(destination.IsStackSlot());
       StoreObject(destination.ToStackSlotAddress(), source.constant());
     }
@@ skipping 19 matching lines @@
   } else if (source.IsStackSlot() && destination.IsRegister()) {
     Exchange(destination.reg(), source.ToStackSlotAddress());
   } else if (source.IsStackSlot() && destination.IsStackSlot()) {
     Exchange(destination.ToStackSlotAddress(), source.ToStackSlotAddress());
   } else if (source.IsFpuRegister() && destination.IsFpuRegister()) {
     __ vmovd(FpuTMP, source.fpu_reg());
     __ vmovd(source.fpu_reg(), destination.fpu_reg());
     __ vmovd(destination.fpu_reg(), FpuTMP);
   } else if (source.IsFpuRegister() || destination.IsFpuRegister()) {
     ASSERT(destination.IsDoubleStackSlot() ||
-           destination.IsFloat32x4StackSlot() ||
-           destination.IsUint32x4StackSlot() ||
+           destination.IsQuadStackSlot() ||
            source.IsDoubleStackSlot() ||
-           source.IsFloat32x4StackSlot() ||
-           source.IsUint32x4StackSlot());
+           source.IsQuadStackSlot());
     bool double_width = destination.IsDoubleStackSlot() ||
                         source.IsDoubleStackSlot();
     DRegister reg = source.IsFpuRegister() ? source.fpu_reg()
                                            : destination.fpu_reg();
     const Address& slot_address = source.IsFpuRegister()
         ? destination.ToStackSlotAddress()
         : source.ToStackSlotAddress();
 
     if (double_width) {
       __ vldrd(FpuTMP, slot_address);
       __ vstrd(reg, slot_address);
       __ vmovd(reg, FpuTMP);
     } else {
       UNIMPLEMENTED();
     }
+  } else if (source.IsDoubleStackSlot() && destination.IsDoubleStackSlot()) {
+    const Address& source_slot_address = source.ToStackSlotAddress();
+    const Address& destination_slot_address = destination.ToStackSlotAddress();
+
+    ScratchFpuRegisterScope ensure_scratch(this, FpuTMP);
+    __ vldrd(FpuTMP, source_slot_address);
+    __ vldrd(ensure_scratch.reg(), destination_slot_address);
+    __ vstrd(FpuTMP, destination_slot_address);
+    __ vstrd(ensure_scratch.reg(), source_slot_address);
+  } else if (source.IsQuadStackSlot() && destination.IsQuadStackSlot()) {
+    UNIMPLEMENTED();
   } else {
     UNREACHABLE();
   }
 
   // The swap of source and destination has executed a move from source to
   // destination.
   move->Eliminate();
 
   // Any unperformed (including pending) move with a source of either
   // this move's source or destination needs to have their source
@@ skipping 24 matching lines @@
 
 void ParallelMoveResolver::Exchange(Register reg, const Address& mem) {
   ASSERT(reg != IP);
   __ mov(IP, ShifterOperand(reg));
   __ ldr(reg, mem);
   __ str(IP, mem);
 }
 
 
 void ParallelMoveResolver::Exchange(const Address& mem1, const Address& mem2) {
-  // TODO(vegorov): allocate temporary registers for such moves.
-  __ Push(R0);
-  __ ldr(R0, mem1);
+  ScratchRegisterScope ensure_scratch(this, IP);

[regis, 2013/04/09 15:29:27]

IP is not an available register, so there is no need to pass it here as blocked
register.
I noticed that some architecture independent code assumes that the range of
available registers starts with register 0, which is not the case on MIPS. That
should be easy for us to fix that.

+  __ ldr(ensure_scratch.reg(), mem1);
   __ ldr(IP, mem2);
+  __ str(ensure_scratch.reg(), mem2);
   __ str(IP, mem1);
-  __ str(R0, mem2);
-  __ Pop(R0);
 }
 
 
+void ParallelMoveResolver::SpillScratch(Register reg) {
+  __ Push(reg);
+}
+
+
+void ParallelMoveResolver::RestoreScratch(Register reg) {
+  __ Pop(reg);
+}
+
+
+void ParallelMoveResolver::SpillFpuScratch(FpuRegister reg) {
+  __ vstrd(reg, Address(SP, -kDoubleSize, Address::PreIndex));
+}
+
+
+void ParallelMoveResolver::RestoreFpuScratch(FpuRegister reg) {
+  __ vldrd(reg, Address(SP, kDoubleSize, Address::PostIndex));
+}
+
+
 #undef __
 
 }  // namespace dart
 
 #endif  // defined TARGET_ARCH_ARM