Subzero. Adds ldrex, strex, and dmb support (ARM32)

Subzero. Adds ldrex, strex, and dmb support (ARM32)

These instructions are used to load/store data atomically, and to
notify the processor about a data memory barrier. They are used for
implementing the llvm.nacl.atomic.* lowerings.

BUG= https://code.google.com/p/nativeclient/issues/detail?id=4076
R=stichnot@chromium.org

Committed: https://gerrit.chromium.org/gerrit/gitweb?p=native_client/pnacl-subzero.git;a=commit;h=16991847500a48932426d979c4f2d4adffaf3649

[John, 2015-10-01 20:57:19]

jpp@chromium.org changed reviewers:
+ kschimpf@google.com, sehr@chromium.org, stichnot@chromium.org

[Jim Stichnoth, 2015-10-01 21:46:47]

lgtm

https://chromiumcodereview.appspot.com/1378303003/diff/1/src/IceInstARM32.cpp
File src/IceInstARM32.cpp (right):

https://chromiumcodereview.appspot.com/1378303003/diff/1/src/IceInstARM32.cpp...
src/IceInstARM32.cpp:1:
//===----------------------------------------------------------------------===//
Why was this changed?

[John, 2015-10-01 22:11:27]

Committed patchset #3 (id:40001) manually as
16991847500a48932426d979c4f2d4adffaf3649 (presubmit successful).

[John, 2015-10-01 22:11:45]

https://chromiumcodereview.appspot.com/1378303003/diff/1/src/IceInstARM32.cpp
File src/IceInstARM32.cpp (right):

https://chromiumcodereview.appspot.com/1378303003/diff/1/src/IceInstARM32.cpp...
src/IceInstARM32.cpp:1:
//===----------------------------------------------------------------------===//
On 2015/10/01 21:46:47, stichnot wrote:
> Why was this changed?

Done.