Index: src/compiler/arm64/instruction-scheduler-arm64.cc |
diff --git a/src/compiler/arm64/instruction-scheduler-arm64.cc b/src/compiler/arm64/instruction-scheduler-arm64.cc |
new file mode 100644 |
index 0000000000000000000000000000000000000000..e50074e925e93a210fb41a4d1003e9a023850979 |
--- /dev/null |
+++ b/src/compiler/arm64/instruction-scheduler-arm64.cc |
@@ -0,0 +1,68 @@ |
+// Copyright 2014 the V8 project authors. All rights reserved. |
+// Use of this source code is governed by a BSD-style license that can be |
+// found in the LICENSE file. |
+ |
+#include "src/compiler/instruction-scheduler.h" |
+ |
+namespace v8 { |
+namespace internal { |
+namespace compiler { |
+ |
+int InstructionScheduler::GetInstructionLatency(const Instruction* instr) { |
+ // Basic latency modeling for arm64 instructions. They have been determined |
+ // in an empirical way. |
+ switch (instr->arch_opcode()) { |
+ case kArm64Float32ToFloat64: |
+ case kArm64Float64ToFloat32: |
+ case kArm64Float64ToInt32: |
+ case kArm64Float64ToUint32: |
+ case kArm64Int32ToFloat64: |
+ case kArm64Uint32ToFloat64: |
+ return 3; |
+ |
+ case kArm64Float64Add: |
+ case kArm64Float64Sub: |
+ return 2; |
+ |
+ case kArm64Float64Mul: |
+ return 3; |
+ |
+ case kArm64Float64Div: |
+ return 6; |
+ |
+ case kArm64Lsl: |
+ case kArm64Lsl32: |
+ case kArm64Lsr: |
+ case kArm64Lsr32: |
+ case kArm64Asr: |
+ case kArm64Asr32: |
+ case kArm64Ror: |
+ case kArm64Ror32: |
+ return 3; |
+ |
+ case kCheckedLoadInt8: |
+ case kCheckedLoadUint8: |
+ case kCheckedLoadInt16: |
+ case kCheckedLoadUint16: |
+ case kCheckedLoadWord32: |
+ case kCheckedLoadWord64: |
+ case kCheckedLoadFloat32: |
+ case kCheckedLoadFloat64: |
+ case kArm64LdrS: |
+ case kArm64LdrD: |
+ case kArm64Ldrb: |
+ case kArm64Ldrsb: |
+ case kArm64Ldrh: |
+ case kArm64Ldrsh: |
+ case kArm64LdrW: |
+ case kArm64Ldr: |
+ return 5; |
+ |
+ default: |
+ return 1; |
+ } |
+} |
+ |
+} // namespace compiler |
+} // namespace internal |
+} // namespace v8 |