Subzero. Enable Atomics in ARM.

src/IceTargetLoweringARM32.h

 //===- subzero/src/IceTargetLoweringARM32.h - ARM32 lowering ----*- C++ -*-===//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 113 matching lines @@
 
   void lowerAlloca(const InstAlloca *Inst) override;
   void lowerArithmetic(const InstArithmetic *Inst) override;
   void lowerAssign(const InstAssign *Inst) override;
   void lowerBr(const InstBr *Inst) override;
   void lowerCall(const InstCall *Inst) override;
   void lowerCast(const InstCast *Inst) override;
   void lowerExtractElement(const InstExtractElement *Inst) override;
   void lowerFcmp(const InstFcmp *Inst) override;
   void lowerIcmp(const InstIcmp *Inst) override;
+  void lowerAtomicRMW(Variable *Dest, uint32_t Operation, Operand *Ptr,
+                      Operand *Val);
   void lowerIntrinsicCall(const InstIntrinsicCall *Inst) override;
   void lowerInsertElement(const InstInsertElement *Inst) override;
   void lowerLoad(const InstLoad *Inst) override;
   void lowerPhi(const InstPhi *Inst) override;
   void lowerRet(const InstRet *Inst) override;
   void lowerSelect(const InstSelect *Inst) override;
   void lowerStore(const InstStore *Inst) override;
   void lowerSwitch(const InstSwitch *Inst) override;
   void lowerUnreachable(const InstUnreachable *Inst) override;
   void prelowerPhis() override;
   void doAddressOptLoad() override;
   void doAddressOptStore() override;
   void randomlyInsertNop(float Probability,
                          RandomNumberGenerator &RNG) override;
 
   enum OperandLegalization {
     Legal_None = 0,
     Legal_Reg = 1 << 0,  /// physical register, not stack location
     Legal_Flex = 1 << 1, /// A flexible operand2, which can hold rotated small
                          /// immediates, or shifted registers.
     Legal_Mem = 1 << 2,  /// includes [r0, r1 lsl #2] as well as [sp, #12]
     Legal_All = ~Legal_None
   };
   using LegalMask = uint32_t;
   Operand *legalize(Operand *From, LegalMask Allowed = Legal_All,
                     int32_t RegNum = Variable::NoRegister);
   Variable *legalizeToReg(Operand *From, int32_t RegNum = Variable::NoRegister);
   OperandARM32Mem *formMemoryOperand(Operand *Ptr, Type Ty);
 
+  Variable64On32 *makeI64RegPair();
   Variable *makeReg(Type Ty, int32_t RegNum = Variable::NoRegister);
   static Type stackSlotType();
   Variable *copyToReg(Operand *Src, int32_t RegNum = Variable::NoRegister);
   void alignRegisterPow2(Variable *Reg, uint32_t Align);
 
   /// Returns a vector in a register with the given constant entries.
   Variable *makeVectorOfZeros(Type Ty, int32_t RegNum = Variable::NoRegister);
 
   void
   makeRandomRegisterPermutation(llvm::SmallVectorImpl<int32_t> &Permutation,
@@ skipping 75 matching lines @@
   }
   /// _ldr, for all your memory to Variable data moves. It handles all types
   /// (integer, floating point, and vectors.) Addr needs to be valid for Dest's
   /// type (e.g., no immediates for vector loads, and no index registers for fp
   /// loads.)
   void _ldr(Variable *Dest, OperandARM32Mem *Addr,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Ldr::create(Func, Dest, Addr, Pred));
   }
   void _ldrex(Variable *Dest, OperandARM32Mem *Addr,
-             CondARM32::Cond Pred = CondARM32::AL) {
-   Context.insert(InstARM32Ldrex::create(Func, Dest, Addr, Pred));
-   if (auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest)) {
-     Context.insert(InstFakeDef::create(Func, Dest64->getLo(), Dest));
-     Context.insert(InstFakeDef::create(Func, Dest64->getHi(), Dest));
-   }
- }
+              CondARM32::Cond Pred = CondARM32::AL) {
+    Context.insert(InstARM32Ldrex::create(Func, Dest, Addr, Pred));
+    if (auto *Dest64 = llvm::dyn_cast<Variable64On32>(Dest)) {
+      Context.insert(InstFakeDef::create(Func, Dest64->getLo(), Dest));
+      Context.insert(InstFakeDef::create(Func, Dest64->getHi(), Dest));
+    }
+  }
   void _lsl(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Lsl::create(Func, Dest, Src0, Src1, Pred));
   }
   void _lsr(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Lsr::create(Func, Dest, Src0, Src1, Pred));
   }
   void _mla(Variable *Dest, Variable *Src0, Variable *Src1, Variable *Acc,
             CondARM32::Cond Pred = CondARM32::AL) {
@@ skipping 17 matching lines @@
     auto *Instr = InstARM32Mov::create(Func, Dest, Src0, Pred);
 
     Context.insert(Instr);
     if (Instr->isMultiDest()) {
       // If Instr is multi-dest, then Dest must be a Variable64On32. We add a
       // fake-def for Instr.DestHi here.
       assert(llvm::isa<Variable64On32>(Dest));
       Context.insert(InstFakeDef::create(Func, Instr->getDestHi()));
     }
   }
+
   void _mov_redefined(Variable *Dest, Operand *Src0,
                       CondARM32::Cond Pred = CondARM32::AL) {
     auto *Instr = InstARM32Mov::create(Func, Dest, Src0, Pred);
     Instr->setDestRedefined();
     Context.insert(Instr);
     if (Instr->isMultiDest()) {
       // If Instr is multi-dest, then Dest must be a Variable64On32. We add a
       // fake-def for Instr.DestHi here.
       assert(llvm::isa<Variable64On32>(Dest));
       Context.insert(InstFakeDef::create(Func, Instr->getDestHi()));
@@ skipping 66 matching lines @@
     Context.insert(InstARM32Sdiv::create(Func, Dest, Src0, Src1, Pred));
   }
   /// _str, for all your Variable to memory transfers. Addr has the same
   /// restrictions that it does in _ldr.
   void _str(Variable *Value, OperandARM32Mem *Addr,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Str::create(Func, Value, Addr, Pred));
   }
   void _strex(Variable *Dest, Variable *Value, OperandARM32Mem *Addr,
               CondARM32::Cond Pred = CondARM32::AL) {
+    // strex requires Dest to be a register other than Value or Addr. This
+    // restriction is cleanly represented by adding an "early definition of of

[Jim Stichnoth, 2015/10/05 22:07:06]

s/of of/of/
Also, should the double-quote be there?  (It's missing the closing
double-quote.)

[John, 2015/10/06 12:03:38]

Done.

+    // Dest (or a latter use of all the sources.)
+    Context.insert(InstFakeDef::create(Func, Dest));
     if (auto *Value64 = llvm::dyn_cast<Variable64On32>(Value)) {
       Context.insert(InstFakeUse::create(Func, Value64->getLo()));
       Context.insert(InstFakeUse::create(Func, Value64->getHi()));
     }
-    Context.insert(InstARM32Strex::create(Func, Dest, Value, Addr, Pred));
+    auto *Instr = InstARM32Strex::create(Func, Dest, Value, Addr, Pred);
+    Context.insert(Instr);
+    Instr->setDestRedefined();

[Jim Stichnoth, 2015/10/05 22:07:06]

What do you think about adding Dest as another Src for the InstARM32Strex
instruction?  That would allow you not to have to call setDestRedefined() here. 
The fewer of those calls the better.

[John, 2015/10/06 12:03:38]

Well, if the method was still named nonkillable, sure, I'd do it. Now that it is
named redefined it precisely tells what's happening here. I'd rather leave this
as is. Besides, I don't want to "leak" liveness requirements down to the InstARM
layer.

   }
   void _sub(Variable *Dest, Variable *Src0, Operand *Src1,
             CondARM32::Cond Pred = CondARM32::AL) {
     Context.insert(InstARM32Sub::create(Func, Dest, Src0, Src1, Pred));
   }
   void _subs(Variable *Dest, Variable *Src0, Operand *Src1,
              CondARM32::Cond Pred = CondARM32::AL) {
     constexpr bool SetFlags = true;
     Context.insert(
         InstARM32Sub::create(Func, Dest, Src0, Src1, Pred, SetFlags));
@@ skipping 169 matching lines @@
 
 private:
   ~TargetHeaderARM32() = default;
 
   TargetARM32Features CPUFeatures;
 };
 
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGARM32_H