Subzero: Improve usability of liveness-related tools.

src/IceTargetLoweringX86BaseImpl.h

 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==//
 //
 //                        The Subzero Code Generator
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 ///
 /// \file
@@ skipping 507 matching lines @@
       // Look for:
       //   a = Load addr
       //   b = <op> a, other
       //   Store b, addr
       // Change to:
       //   a = Load addr
       //   b = <op> a, other
       //   x = FakeDef
       //   RMW <op>, addr, other, x
       //   b = Store b, addr, x
-      // Note that inferTwoAddress() makes sure setDestNonKillable() gets
-      // called on the updated Store instruction, to avoid liveness problems
-      // later.
+      // Note that inferTwoAddress() makes sure setDestRedefined() gets called
+      // on the updated Store instruction, to avoid liveness problems later.
       //
       // With this transformation, the Store instruction acquires a Dest
       // variable and is now subject to dead code elimination if there are no
-      // more uses of "b".  Variable "x" is a beacon for determining whether
-      // the Store instruction gets dead-code eliminated.  If the Store
-      // instruction is eliminated, then it must be the case that the RMW
-      // instruction ends x's live range, and therefore the RMW instruction
-      // will be retained and later lowered.  On the other hand, if the RMW
-      // instruction does not end x's live range, then the Store instruction
-      // must still be present, and therefore the RMW instruction is ignored
-      // during lowering because it is redundant with the Store instruction.
+      // more uses of "b".  Variable "x" is a beacon for determining whether the
+      // Store instruction gets dead-code eliminated.  If the Store instruction
+      // is eliminated, then it must be the case that the RMW instruction ends
+      // x's live range, and therefore the RMW instruction will be retained and
+      // later lowered.  On the other hand, if the RMW instruction does not end
+      // x's live range, then the Store instruction must still be present, and
+      // therefore the RMW instruction is ignored during lowering because it is
+      // redundant with the Store instruction.
       //
       // Note that if "a" has further uses, the RMW transformation may still
       // trigger, resulting in two loads and one store, which is worse than the
       // original one load and one store.  However, this is probably rare, and
       // caching probably keeps it just as fast.
       if (!isSameMemAddressOperand<Machine>(Load->getSourceAddress(),
                                             Store->getAddr()))
         continue;
       Operand *ArithSrcFromLoad = Arith->getSrc(0);
       Operand *ArithSrcOther = Arith->getSrc(1);
@@ skipping 475 matching lines @@
   // somewhat arbitrary choice of 3.
   const uint32_t MaxOpsForOptimizedMul = 3;
   if (CountOps > MaxOpsForOptimizedMul)
     return false;
   _mov(T, Src0);
   Constant *Zero = Ctx->getConstantZero(IceType_i32);
   for (uint32_t i = 0; i < Count9; ++i) {
     const uint16_t Shift = 3; // log2(9-1)
     _lea(T,
          Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
-    _set_dest_nonkillable();
   }
   for (uint32_t i = 0; i < Count5; ++i) {
     const uint16_t Shift = 2; // log2(5-1)
     _lea(T,
          Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
-    _set_dest_nonkillable();
   }
   for (uint32_t i = 0; i < Count3; ++i) {
     const uint16_t Shift = 1; // log2(3-1)
     _lea(T,
          Traits::X86OperandMem::create(Func, IceType_void, T, Zero, T, Shift));
-    _set_dest_nonkillable();
   }
   if (Count2) {
     _shl(T, Ctx->getConstantInt(Ty, Count2));
   }
   if (Src1IsNegative)
     _neg(T);
   _mov(Dest, T);
   return true;
 }
 
@@ skipping 149 matching lines @@
       //   t2 = shl t2, t1
       //   test t1, 0x20
       //   je L1
       //   use(t3)
       //   t3 = t2
       //   t2 = 0
       _shld(T_3, T_2, T_1);
       _shl(T_2, T_1);
       _test(T_1, BitTest);
       _br(Traits::Cond::Br_e, Label);
-      // T_2 and T_3 are being assigned again because of the intra-block
-      // control flow, so we need the _mov_nonkillable variant to avoid
-      // liveness problems.
-      _mov_nonkillable(T_3, T_2);
-      _mov_nonkillable(T_2, Zero);
+      // T_2 and T_3 are being assigned again because of the intra-block control
+      // flow, so we need the _mov_redefined variant to avoid liveness problems.
+      _mov_redefined(T_3, T_2);
+      _mov_redefined(T_2, Zero);
     } break;
     case InstArithmetic::Lshr: {
       // a=b>>c (unsigned) ==>
       //   t2 = shrd t2, t3, t1
       //   t3 = shr t3, t1
       //   test t1, 0x20
       //   je L1
       //   use(t2)
       //   t2 = t3
       //   t3 = 0
       _shrd(T_2, T_3, T_1);
       _shr(T_3, T_1);
       _test(T_1, BitTest);
       _br(Traits::Cond::Br_e, Label);
-      // T_2 and T_3 are being assigned again because of the intra-block
-      // control flow, so we need the _mov_nonkillable variant to avoid
-      // liveness problems.
-      _mov_nonkillable(T_2, T_3);
-      _mov_nonkillable(T_3, Zero);
+      // T_2 and T_3 are being assigned again because of the intra-block control
+      // flow, so we need the _mov_redefined variant to avoid liveness problems.
+      _mov_redefined(T_2, T_3);
+      _mov_redefined(T_3, Zero);
     } break;
     case InstArithmetic::Ashr: {
       // a=b>>c (signed) ==>
       //   t2 = shrd t2, t3, t1
       //   t3 = sar t3, t1
       //   test t1, 0x20
       //   je L1
       //   use(t2)
       //   t2 = t3
       //   t3 = sar t3, 0x1f
       Constant *SignExtend = Ctx->getConstantInt32(0x1f);
       _shrd(T_2, T_3, T_1);
       _sar(T_3, T_1);
       _test(T_1, BitTest);
       _br(Traits::Cond::Br_e, Label);
-      // T_2 and T_3 are being assigned again because of the intra-block
-      // control flow, so T_2 needs the _mov_nonkillable variant to avoid
-      // liveness problems. T_3 doesn't need special treatment because it is
-      // reassigned via _sar instead of _mov.
-      _mov_nonkillable(T_2, T_3);
+      // T_2 and T_3 are being assigned again because of the intra-block control
+      // flow, so T_2 needs the _mov_redefined variant to avoid liveness
+      // problems. T_3 doesn't need special treatment because it is reassigned
+      // via _sar instead of _mov.
+      _mov_redefined(T_2, T_3);
       _sar(T_3, SignExtend);
     } break;
     }
     // COMMON SUFFIX OF: a=b SHIFT_OP c ==>
     // L1:
     //   a.lo = t2
     //   a.hi = t3
     Context.insert(Label);
     _mov(DestLo, T_2);
     _mov(DestHi, T_3);
@@ skipping 1335 matching lines @@
   _mov(Dest, Default);
   if (HasC1) {
     typename Traits::Insts::Label *Label =
         Traits::Insts::Label::create(Func, this);
     _br(Traits::TableFcmp[Index].C1, Label);
     if (HasC2) {
       _br(Traits::TableFcmp[Index].C2, Label);
     }
     Constant *NonDefault =
         Ctx->getConstantInt32(!Traits::TableFcmp[Index].Default);
-    _mov_nonkillable(Dest, NonDefault);
+    _mov_redefined(Dest, NonDefault);
     Context.insert(Label);
   }
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerIcmp(const InstIcmp *Inst) {
   Operand *Src0 = legalize(Inst->getSrc(0));
   Operand *Src1 = legalize(Inst->getSrc(1));
   Variable *Dest = Inst->getDest();
 
@@ skipping 140 matching lines @@
       Traits::Insts::Label::create(Func, this);
   _mov(Dest, One);
   _cmp(Src0HiRM, Src1HiRI);
   if (Traits::TableIcmp64[Index].C1 != Traits::Cond::Br_None)
     _br(Traits::TableIcmp64[Index].C1, LabelTrue);
   if (Traits::TableIcmp64[Index].C2 != Traits::Cond::Br_None)
     _br(Traits::TableIcmp64[Index].C2, LabelFalse);
   _cmp(Src0LoRM, Src1LoRI);
   _br(Traits::TableIcmp64[Index].C3, LabelTrue);
   Context.insert(LabelFalse);
-  _mov_nonkillable(Dest, Zero);
+  _mov_redefined(Dest, Zero);
   Context.insert(LabelTrue);
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::lowerInsertElement(const InstInsertElement *Inst) {
   Operand *SourceVectNotLegalized = Inst->getSrc(0);
   Operand *ElementToInsertNotLegalized = Inst->getSrc(1);
   ConstantInteger32 *ElementIndex =
       llvm::dyn_cast<ConstantInteger32>(Inst->getSrc(2));
   // Only constant indices are allowed in PNaCl IR.
@@ skipping 452 matching lines @@
   case Intrinsics::Stacksave: {
     Variable *esp =
         Func->getTarget()->getPhysicalRegister(Traits::RegisterSet::Reg_esp);
     Variable *Dest = Instr->getDest();
     _mov(Dest, esp);
     return;
   }
   case Intrinsics::Stackrestore: {
     Variable *esp =
         Func->getTarget()->getPhysicalRegister(Traits::RegisterSet::Reg_esp);
-    _mov_nonkillable(esp, Instr->getArg(0));
+    _mov_redefined(esp, Instr->getArg(0));
     return;
   }
   case Intrinsics::Trap:
     _ud2();
     return;
   case Intrinsics::UnknownIntrinsic:
     Func->setError("Should not be lowering UnknownIntrinsic");
     return;
   }
   return;
@@ skipping 1118 matching lines @@
   if (typeWidthInBytes(DestTy) == 1 || isFloatingType(DestTy)) {
     // The cmov instruction doesn't allow 8-bit or FP operands, so we need
     // explicit control flow.
     // d=cmp e,f; a=d?b:c ==> cmp e,f; a=b; jne L1; a=c; L1:
     typename Traits::Insts::Label *Label =
         Traits::Insts::Label::create(Func, this);
     SrcT = legalize(SrcT, Legal_Reg | Legal_Imm);
     _mov(Dest, SrcT);
     _br(Cond, Label);
     SrcF = legalize(SrcF, Legal_Reg | Legal_Imm);
-    _mov_nonkillable(Dest, SrcF);
+    _mov_redefined(Dest, SrcF);
     Context.insert(Label);
     return;
   }
   // mov t, SrcF; cmov_cond t, SrcT; mov dest, t
   // But if SrcT is immediate, we might be able to do better, as the cmov
   // instruction doesn't allow an immediate operand:
   // mov t, SrcT; cmov_!cond t, SrcF; mov dest, t
   if (llvm::isa<Constant>(SrcT) && !llvm::isa<Constant>(SrcF)) {
     std::swap(SrcT, SrcF);
     Cond = InstX86Base<Machine>::getOppositeCondition(Cond);
@@ skipping 815 matching lines @@
     ++TyIndex;
   uint32_t MaxIndex = MaxSize == NoSizeLimit
                           ? llvm::array_lengthof(TypeForSize) - 1
                           : llvm::findLastSet(MaxSize, llvm::ZB_Undefined);
   return TypeForSize[std::min(TyIndex, MaxIndex)];
 }
 
 template <class Machine> void TargetX86Base<Machine>::postLower() {
   if (Ctx->getFlags().getOptLevel() == Opt_m1)
     return;
-  inferTwoAddress();
+  markRedefinitions();
 }
 
 template <class Machine>
 void TargetX86Base<Machine>::makeRandomRegisterPermutation(
     llvm::SmallVectorImpl<int32_t> &Permutation,
     const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const {
   Traits::makeRandomRegisterPermutation(Ctx, Func, Permutation,
                                         ExcludeRegisters, Salt);
 }
 
@@ skipping 66 matching lines @@
       // chain. So we add RegNum argument here. Note we use 'lea' instruction
       // instead of 'xor' to avoid affecting the flags.
       Variable *Reg = makeReg(IceType_i32, RegNum);
       ConstantInteger32 *Integer = llvm::cast<ConstantInteger32>(Immediate);
       uint32_t Value = Integer->getValue();
       uint32_t Cookie = Func->getConstantBlindingCookie();
       _mov(Reg, Ctx->getConstantInt(IceType_i32, Cookie + Value));
       Constant *Offset = Ctx->getConstantInt(IceType_i32, 0 - Cookie);
       _lea(Reg, Traits::X86OperandMem::create(Func, IceType_i32, Reg, Offset,
                                               nullptr, 0));
-      // make sure liveness analysis won't kill this variable, otherwise a
-      // liveness assertion will be triggered.
-      _set_dest_nonkillable();
       if (Immediate->getType() != IceType_i32) {
         Variable *TruncReg = makeReg(Immediate->getType(), RegNum);
         _mov(TruncReg, Reg);
         return TruncReg;
       }
       return Reg;
     }
     if (Ctx->getFlags().getRandomizeAndPoolImmediatesOption() == RPI_Pool) {
       // pool the constant
       // FROM:
@@ skipping 66 matching lines @@
 
         typename Traits::X86OperandMem *TempMemOperand =
             Traits::X86OperandMem::create(Func, MemOperand->getType(),
                                           MemOperand->getBase(), Mask1);
         // If we have already assigned a physical register, we must come from
         // advancedPhiLowering()=>lowerAssign(). In this case we should reuse
         // the assigned register as this assignment is that start of its
         // use-def chain. So we add RegNum argument here.
         Variable *RegTemp = makeReg(MemOperand->getOffset()->getType(), RegNum);
         _lea(RegTemp, TempMemOperand);
-        // As source operand doesn't use the dstreg, we don't need to add
-        // _set_dest_nonkillable(). But if we use the same Dest Reg, that is,
-        // with RegNum assigned, we should add this _set_dest_nonkillable()
-        if (RegNum != Variable::NoRegister)
-          _set_dest_nonkillable();
 
         typename Traits::X86OperandMem *NewMemOperand =
             Traits::X86OperandMem::create(Func, MemOperand->getType(), RegTemp,
                                           Mask2, MemOperand->getIndex(),
                                           MemOperand->getShift(),
                                           MemOperand->getSegmentRegister());
 
         // Label this memory operand as randomized, so we won't randomize it
         // again in case we call legalize() multiple times on this memory
         // operand.
@@ skipping 32 matching lines @@
         _mov(RegTemp, SymbolOperand);
         // If we have a base variable here, we should add the lea instruction
         // to add the value of the base variable to RegTemp. If there is no
         // base variable, we won't need this lea instruction.
         if (MemOperand->getBase()) {
           typename Traits::X86OperandMem *CalculateOperand =
               Traits::X86OperandMem::create(
                   Func, MemOperand->getType(), MemOperand->getBase(), nullptr,
                   RegTemp, 0, MemOperand->getSegmentRegister());
           _lea(RegTemp, CalculateOperand);
-          _set_dest_nonkillable();
         }
         typename Traits::X86OperandMem *NewMemOperand =
             Traits::X86OperandMem::create(Func, MemOperand->getType(), RegTemp,
                                           nullptr, MemOperand->getIndex(),
                                           MemOperand->getShift(),
                                           MemOperand->getSegmentRegister());
         return NewMemOperand;
       }
       assert("Unsupported -randomize-pool-immediates option" && false);
     }
   }
   // the offset is not eligible for blinding or pooling, return the original
   // mem operand
   return MemOperand;
 }
 
 } // end of namespace X86Internal
 } // end of namespace Ice
 
 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H