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1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// | 1 //===- subzero/src/IceTargetLoweringMIPS32.cpp - MIPS32 lowering ----------===// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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651 // integrity of liveness analysis. Undef values are also turned into zeroes, | 651 // integrity of liveness analysis. Undef values are also turned into zeroes, |
652 // since loOperand() and hiOperand() don't expect Undef input. | 652 // since loOperand() and hiOperand() don't expect Undef input. |
653 void TargetMIPS32::prelowerPhis() { | 653 void TargetMIPS32::prelowerPhis() { |
654 UnimplementedError(Func->getContext()->getFlags()); | 654 UnimplementedError(Func->getContext()->getFlags()); |
655 } | 655 } |
656 | 656 |
657 void TargetMIPS32::postLower() { | 657 void TargetMIPS32::postLower() { |
658 if (Ctx->getFlags().getOptLevel() == Opt_m1) | 658 if (Ctx->getFlags().getOptLevel() == Opt_m1) |
659 return; | 659 return; |
660 // Find two-address non-SSA instructions where Dest==Src0, and set the | 660 // Find two-address non-SSA instructions where Dest==Src0, and set the |
661 // DestNonKillable flag to keep liveness analysis consistent. | 661 // IsDestRedefined flag to keep liveness analysis consistent. |
662 UnimplementedError(Func->getContext()->getFlags()); | 662 UnimplementedError(Func->getContext()->getFlags()); |
663 } | 663 } |
664 | 664 |
665 void TargetMIPS32::makeRandomRegisterPermutation( | 665 void TargetMIPS32::makeRandomRegisterPermutation( |
666 llvm::SmallVectorImpl<int32_t> &Permutation, | 666 llvm::SmallVectorImpl<int32_t> &Permutation, |
667 const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const { | 667 const llvm::SmallBitVector &ExcludeRegisters, uint64_t Salt) const { |
668 (void)Permutation; | 668 (void)Permutation; |
669 (void)ExcludeRegisters; | 669 (void)ExcludeRegisters; |
670 (void)Salt; | 670 (void)Salt; |
671 UnimplementedError(Func->getContext()->getFlags()); | 671 UnimplementedError(Func->getContext()->getFlags()); |
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713 void TargetDataMIPS32::lowerJumpTables() { | 713 void TargetDataMIPS32::lowerJumpTables() { |
714 if (Ctx->getFlags().getDisableTranslation()) | 714 if (Ctx->getFlags().getDisableTranslation()) |
715 return; | 715 return; |
716 UnimplementedError(Ctx->getFlags()); | 716 UnimplementedError(Ctx->getFlags()); |
717 } | 717 } |
718 | 718 |
719 TargetHeaderMIPS32::TargetHeaderMIPS32(GlobalContext *Ctx) | 719 TargetHeaderMIPS32::TargetHeaderMIPS32(GlobalContext *Ctx) |
720 : TargetHeaderLowering(Ctx) {} | 720 : TargetHeaderLowering(Ctx) {} |
721 | 721 |
722 } // end of namespace Ice | 722 } // end of namespace Ice |
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