VM: Initialize Instruction objects with break instructions instead of null.

runtime/vm/assembler_arm64.h

 // Copyright (c) 2014, the Dart project authors.  Please see the AUTHORS file
 // for details. All rights reserved. Use of this source code is governed by a
 // BSD-style license that can be found in the LICENSE file.
 
 #ifndef VM_ASSEMBLER_ARM64_H_
 #define VM_ASSEMBLER_ARM64_H_
 
 #ifndef VM_ASSEMBLER_H_
 #error Do not include assembler_arm64.h directly; use assembler.h instead.
 #endif
@@ skipping 820 matching lines @@
   }
   void ret(Register rn = R30) {
     EmitUnconditionalBranchRegOp(RET, rn);
   }
 
   // Breakpoint.
   void brk(uint16_t imm) {
     EmitExceptionGenOp(BRK, imm);
   }
 
+  static uword GetBreakInstructionFiller() {
+    const intptr_t encoding = ExceptionGenOpEncoding(BRK, 0);
+    return encoding << 32 | encoding;
+  }
+
   // Double floating point.
   bool fmovdi(VRegister vd, double immd) {
     int64_t imm64 = bit_cast<int64_t, double>(immd);
     const uint8_t bit7 = imm64 >> 63;
     const uint8_t bit6 = (~(imm64 >> 62)) & 0x1;
     const uint8_t bit54 = (imm64 >> 52) & 0x3;
     const uint8_t bit30 = (imm64 >> 48) & 0xf;
     const uint8_t imm8 = (bit7 << 7) | (bit6 << 6) | (bit54 << 4) | bit30;
     const int64_t expimm8 = Instr::VFPExpandImm(imm8);
     if (imm64 != expimm8) {
@@ skipping 830 matching lines @@
   }
 
   void EmitUnconditionalBranchRegOp(UnconditionalBranchRegOp op, Register rn) {
     ASSERT((rn != CSP) && (rn != R31));
     const Register crn = ConcreteRegister(rn);
     const int32_t encoding =
         op | (static_cast<int32_t>(crn) << kRnShift);
     Emit(encoding);
   }
 
+  static int32_t ExceptionGenOpEncoding(ExceptionGenOp op, uint16_t imm) {
+    return op | (static_cast<int32_t>(imm) << kImm16Shift);
+  }
+
   void EmitExceptionGenOp(ExceptionGenOp op, uint16_t imm) {
-    const int32_t encoding =
-        op | (static_cast<int32_t>(imm) << kImm16Shift);
-    Emit(encoding);
+    Emit(ExceptionGenOpEncoding(op, imm));
   }
 
   void EmitMoveWideOp(MoveWideOp op, Register rd, const Immediate& imm,
                       int hw_idx, OperandSize sz) {
     ASSERT((hw_idx >= 0) && (hw_idx <= 3));
     ASSERT((sz == kDoubleWord) || (sz == kWord) || (sz == kUnsignedWord));
     const int32_t size = (sz == kDoubleWord) ? B31 : 0;
     const int32_t encoding =
         op | size |
         (static_cast<int32_t>(rd) << kRdShift) |
@@ skipping 215 matching lines @@
                                   Register value,
                                   Label* no_update);
 
   DISALLOW_ALLOCATION();
   DISALLOW_COPY_AND_ASSIGN(Assembler);
 };
 
 }  // namespace dart
 
 #endif  // VM_ASSEMBLER_ARM64_H_