| Index: src/IceAssemblerX86BaseImpl.h
|
| diff --git a/src/IceAssemblerX86BaseImpl.h b/src/IceAssemblerX86BaseImpl.h
|
| index b1013d640b11146abf8dea49c8a2d9cf7a3d6d09..cfbf52a106b11bdcc7bae2e0e61b5c78bc19b4b5 100644
|
| --- a/src/IceAssemblerX86BaseImpl.h
|
| +++ b/src/IceAssemblerX86BaseImpl.h
|
| @@ -2581,6 +2581,50 @@ void AssemblerX86Base<Machine>::imul(Type Ty,
|
| }
|
|
|
| template <class Machine>
|
| +void AssemblerX86Base<Machine>::imul_imm(Type Ty,
|
| + typename Traits::GPRRegister dst,
|
| + typename Traits::GPRRegister src,
|
| + const Immediate &imm) {
|
| + AssemblerBuffer::EnsureCapacity ensured(&Buffer);
|
| + assert(Ty == IceType_i16 || Ty == IceType_i32);
|
| + if (Ty == IceType_i16)
|
| + emitOperandSizeOverride();
|
| + emitRexRB(Ty, dst, src);
|
| + if (imm.is_int8()) {
|
| + emitUint8(0x6B);
|
| + emitRegisterOperand(gprEncoding(dst), gprEncoding(src));
|
| + emitUint8(imm.value() & 0xFF);
|
| + } else {
|
| + emitUint8(0x69);
|
| + emitRegisterOperand(gprEncoding(dst), gprEncoding(src));
|
| + emitImmediate(Ty, imm);
|
| + }
|
| +}
|
| +
|
| +template <class Machine>
|
| +void AssemblerX86Base<Machine>::imul_imm(Type Ty,
|
| + typename Traits::GPRRegister dst,
|
| + const typename Traits::Address
|
| + &address,
|
| + const Immediate &imm) {
|
| + AssemblerBuffer::EnsureCapacity ensured(&Buffer);
|
| + assert(Ty == IceType_i16 || Ty == IceType_i32);
|
| + if (Ty == IceType_i16)
|
| + emitOperandSizeOverride();
|
| + emitRex(Ty, address, dst);
|
| + if (imm.is_int8()) {
|
| + emitUint8(0x6B);
|
| + emitOperand(gprEncoding(dst), address);
|
| + emitUint8(imm.value() & 0xFF);
|
| + } else {
|
| + emitUint8(0x69);
|
| + emitOperand(gprEncoding(dst), address);
|
| + emitImmediate(Ty, imm);
|
| + }
|
| + emitImmediate(Ty, imm);
|
| +}
|
| +
|
| +template <class Machine>
|
| void AssemblerX86Base<Machine>::mul(Type Ty, typename Traits::GPRRegister reg) {
|
| AssemblerBuffer::EnsureCapacity ensured(&Buffer);
|
| if (Ty == IceType_i16)
|
|
|