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1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=// | 1 //===- subzero/src/IceAssemblerX86BaseImpl.h - base x86 assembler -*- C++ -*-=// |
2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file | 2 // Copyright (c) 2013, the Dart project authors. Please see the AUTHORS file |
3 // for details. All rights reserved. Use of this source code is governed by a | 3 // for details. All rights reserved. Use of this source code is governed by a |
4 // BSD-style license that can be found in the LICENSE file. | 4 // BSD-style license that can be found in the LICENSE file. |
5 // | 5 // |
6 // Modified by the Subzero authors. | 6 // Modified by the Subzero authors. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 // | 9 // |
10 // The Subzero Code Generator | 10 // The Subzero Code Generator |
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2574 emitOperandSizeOverride(); | 2574 emitOperandSizeOverride(); |
2575 emitRex(Ty, address, RexRegIrrelevant); | 2575 emitRex(Ty, address, RexRegIrrelevant); |
2576 if (isByteSizedArithType(Ty)) | 2576 if (isByteSizedArithType(Ty)) |
2577 emitUint8(0xF6); | 2577 emitUint8(0xF6); |
2578 else | 2578 else |
2579 emitUint8(0xF7); | 2579 emitUint8(0xF7); |
2580 emitOperand(5, address); | 2580 emitOperand(5, address); |
2581 } | 2581 } |
2582 | 2582 |
2583 template <class Machine> | 2583 template <class Machine> |
| 2584 void AssemblerX86Base<Machine>::imul(Type Ty, typename Traits::GPRRegister dst, |
| 2585 typename Traits::GPRRegister src, |
| 2586 const Immediate &imm) { |
| 2587 AssemblerBuffer::EnsureCapacity ensured(&Buffer); |
| 2588 assert(Ty == IceType_i16 || Ty == IceType_i32); |
| 2589 if (Ty == IceType_i16) |
| 2590 emitOperandSizeOverride(); |
| 2591 emitRexRB(Ty, dst, src); |
| 2592 if (imm.is_int8()) { |
| 2593 emitUint8(0x6B); |
| 2594 emitRegisterOperand(gprEncoding(dst), gprEncoding(src)); |
| 2595 emitUint8(imm.value() & 0xFF); |
| 2596 } else { |
| 2597 emitUint8(0x69); |
| 2598 emitRegisterOperand(gprEncoding(dst), gprEncoding(src)); |
| 2599 emitImmediate(Ty, imm); |
| 2600 } |
| 2601 } |
| 2602 |
| 2603 template <class Machine> |
| 2604 void AssemblerX86Base<Machine>::imul(Type Ty, typename Traits::GPRRegister dst, |
| 2605 const typename Traits::Address &address, |
| 2606 const Immediate &imm) { |
| 2607 AssemblerBuffer::EnsureCapacity ensured(&Buffer); |
| 2608 assert(Ty == IceType_i16 || Ty == IceType_i32); |
| 2609 if (Ty == IceType_i16) |
| 2610 emitOperandSizeOverride(); |
| 2611 emitRex(Ty, address, dst); |
| 2612 if (imm.is_int8()) { |
| 2613 emitUint8(0x6B); |
| 2614 emitOperand(gprEncoding(dst), address); |
| 2615 emitUint8(imm.value() & 0xFF); |
| 2616 } else { |
| 2617 emitUint8(0x69); |
| 2618 emitOperand(gprEncoding(dst), address); |
| 2619 emitImmediate(Ty, imm); |
| 2620 } |
| 2621 } |
| 2622 |
| 2623 template <class Machine> |
2584 void AssemblerX86Base<Machine>::mul(Type Ty, typename Traits::GPRRegister reg) { | 2624 void AssemblerX86Base<Machine>::mul(Type Ty, typename Traits::GPRRegister reg) { |
2585 AssemblerBuffer::EnsureCapacity ensured(&Buffer); | 2625 AssemblerBuffer::EnsureCapacity ensured(&Buffer); |
2586 if (Ty == IceType_i16) | 2626 if (Ty == IceType_i16) |
2587 emitOperandSizeOverride(); | 2627 emitOperandSizeOverride(); |
2588 emitRexB(Ty, reg); | 2628 emitRexB(Ty, reg); |
2589 if (isByteSizedArithType(Ty)) | 2629 if (isByteSizedArithType(Ty)) |
2590 emitUint8(0xF6); | 2630 emitUint8(0xF6); |
2591 else | 2631 else |
2592 emitUint8(0xF7); | 2632 emitUint8(0xF7); |
2593 emitRegisterOperand(4, gprEncoding(reg)); | 2633 emitRegisterOperand(4, gprEncoding(reg)); |
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3396 (void)shifter; | 3436 (void)shifter; |
3397 if (Ty == IceType_i16) | 3437 if (Ty == IceType_i16) |
3398 emitOperandSizeOverride(); | 3438 emitOperandSizeOverride(); |
3399 emitRexB(Ty, operand.rm()); | 3439 emitRexB(Ty, operand.rm()); |
3400 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3); | 3440 emitUint8(isByteSizedArithType(Ty) ? 0xD2 : 0xD3); |
3401 emitOperand(rm, operand); | 3441 emitOperand(rm, operand); |
3402 } | 3442 } |
3403 | 3443 |
3404 } // end of namespace X86Internal | 3444 } // end of namespace X86Internal |
3405 } // end of namespace Ice | 3445 } // end of namespace Ice |
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