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1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// | 1 //===- subzero/src/IceTargetLoweringX86BaseImpl.h - x86 lowering -*- C++ -*-==// |
2 // | 2 // |
3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
4 // | 4 // |
5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
7 // | 7 // |
8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
9 /// | 9 /// |
10 /// \file | 10 /// \file |
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1596 case InstArithmetic::Mul: | 1596 case InstArithmetic::Mul: |
1597 if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) { | 1597 if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) { |
1598 if (optimizeScalarMul(Dest, Src0, C->getValue())) | 1598 if (optimizeScalarMul(Dest, Src0, C->getValue())) |
1599 return; | 1599 return; |
1600 } | 1600 } |
1601 // The 8-bit version of imul only allows the form "imul r/m8" where T must | 1601 // The 8-bit version of imul only allows the form "imul r/m8" where T must |
1602 // be in eax. | 1602 // be in eax. |
1603 if (isByteSizedArithType(Dest->getType())) { | 1603 if (isByteSizedArithType(Dest->getType())) { |
1604 _mov(T, Src0, Traits::RegisterSet::Reg_eax); | 1604 _mov(T, Src0, Traits::RegisterSet::Reg_eax); |
1605 Src1 = legalize(Src1, Legal_Reg | Legal_Mem); | 1605 Src1 = legalize(Src1, Legal_Reg | Legal_Mem); |
| 1606 _imul(T, Src1); |
| 1607 _mov(Dest, T); |
| 1608 } else if (auto *ImmConst = llvm::dyn_cast<ConstantInteger32>(Src1)) { |
| 1609 T = makeReg(Dest->getType()); |
| 1610 _imul_imm(T, Src0, ImmConst); |
| 1611 _mov(Dest, T); |
1606 } else { | 1612 } else { |
1607 _mov(T, Src0); | 1613 _mov(T, Src0); |
| 1614 _imul(T, Src1); |
| 1615 _mov(Dest, T); |
1608 } | 1616 } |
1609 _imul(T, Src1); | |
1610 _mov(Dest, T); | |
1611 break; | 1617 break; |
1612 case InstArithmetic::Shl: | 1618 case InstArithmetic::Shl: |
1613 _mov(T, Src0); | 1619 _mov(T, Src0); |
1614 if (!llvm::isa<ConstantInteger32>(Src1)) | 1620 if (!llvm::isa<ConstantInteger32>(Src1)) |
1615 Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx); | 1621 Src1 = legalizeToReg(Src1, Traits::RegisterSet::Reg_ecx); |
1616 _shl(T, Src1); | 1622 _shl(T, Src1); |
1617 _mov(Dest, T); | 1623 _mov(Dest, T); |
1618 break; | 1624 break; |
1619 case InstArithmetic::Lshr: | 1625 case InstArithmetic::Lshr: |
1620 _mov(T, Src0); | 1626 _mov(T, Src0); |
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5471 } | 5477 } |
5472 // the offset is not eligible for blinding or pooling, return the original | 5478 // the offset is not eligible for blinding or pooling, return the original |
5473 // mem operand | 5479 // mem operand |
5474 return MemOperand; | 5480 return MemOperand; |
5475 } | 5481 } |
5476 | 5482 |
5477 } // end of namespace X86Internal | 5483 } // end of namespace X86Internal |
5478 } // end of namespace Ice | 5484 } // end of namespace Ice |
5479 | 5485 |
5480 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H | 5486 #endif // SUBZERO_SRC_ICETARGETLOWERINGX86BASEIMPL_H |
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