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Issue 1365073002: Revert of Remove register index/code indirection (Closed) Base URL: https://chromium.googlesource.com/v8/v8.git@master
Patch Set: Created 5 years, 2 months ago
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1 // Copyright 2012 the V8 project authors. All rights reserved. 1 // Copyright 2012 the V8 project authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be 2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file. 3 // found in the LICENSE file.
4 4
5 #include "src/x64/assembler-x64.h" 5 #include "src/x64/assembler-x64.h"
6 6
7 #include <cstring> 7 #include <cstring>
8 8
9 #if V8_TARGET_ARCH_X64 9 #if V8_TARGET_ARCH_X64
10 10
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109 "POPCNT=%d ATOM=%d\n", 109 "POPCNT=%d ATOM=%d\n",
110 CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSE4_1), 110 CpuFeatures::IsSupported(SSE3), CpuFeatures::IsSupported(SSE4_1),
111 CpuFeatures::IsSupported(SAHF), CpuFeatures::IsSupported(AVX), 111 CpuFeatures::IsSupported(SAHF), CpuFeatures::IsSupported(AVX),
112 CpuFeatures::IsSupported(FMA3), CpuFeatures::IsSupported(BMI1), 112 CpuFeatures::IsSupported(FMA3), CpuFeatures::IsSupported(BMI1),
113 CpuFeatures::IsSupported(BMI2), CpuFeatures::IsSupported(LZCNT), 113 CpuFeatures::IsSupported(BMI2), CpuFeatures::IsSupported(LZCNT),
114 CpuFeatures::IsSupported(POPCNT), CpuFeatures::IsSupported(ATOM)); 114 CpuFeatures::IsSupported(POPCNT), CpuFeatures::IsSupported(ATOM));
115 } 115 }
116 116
117 117
118 // ----------------------------------------------------------------------------- 118 // -----------------------------------------------------------------------------
119 // Register constants.
120
121 const int
122 Register::kRegisterCodeByAllocationIndex[kMaxNumAllocatableRegisters] = {
123 // rax, rbx, rdx, rcx, rsi, rdi, r8, r9, r11, r12, r14, r15
124 0, 3, 2, 1, 6, 7, 8, 9, 11, 12, 14, 15
125 };
126
127 const int Register::kAllocationIndexByRegisterCode[kNumRegisters] = {
128 0, 3, 2, 1, -1, -1, 4, 5, 6, 7, -1, 8, 9, -1, 10, 11
129 };
130
131
132 // -----------------------------------------------------------------------------
119 // Implementation of Operand 133 // Implementation of Operand
120 134
121 Operand::Operand(Register base, int32_t disp) : rex_(0) { 135 Operand::Operand(Register base, int32_t disp) : rex_(0) {
122 len_ = 1; 136 len_ = 1;
123 if (base.is(rsp) || base.is(r12)) { 137 if (base.is(rsp) || base.is(r12)) {
124 // SIB byte is needed to encode (rsp + offset) or (r12 + offset). 138 // SIB byte is needed to encode (rsp + offset) or (r12 + offset).
125 set_sib(times_1, rsp, base); 139 set_sib(times_1, rsp, base);
126 } 140 }
127 141
128 if (disp == 0 && !base.is(rbp) && !base.is(r13)) { 142 if (disp == 0 && !base.is(rbp) && !base.is(r13)) {
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3929 3943
3930 bool RelocInfo::IsInConstantPool() { 3944 bool RelocInfo::IsInConstantPool() {
3931 return false; 3945 return false;
3932 } 3946 }
3933 3947
3934 3948
3935 } // namespace internal 3949 } // namespace internal
3936 } // namespace v8 3950 } // namespace v8
3937 3951
3938 #endif // V8_TARGET_ARCH_X64 3952 #endif // V8_TARGET_ARCH_X64
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