Subzero: Improve handling of alloca instructions of constant size.

tests_lit/llvm2ice_tests/nacl-atomic-intrinsics.ll

 ; This tests each of the supported NaCl atomic instructions for every
 ; size allowed.
 
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   | FileCheck %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -O2 \
 ; RUN:   | FileCheck --check-prefix=O2 %s
 ; RUN: %p2i -i %s --filetype=obj --disassemble --args -Om1 \
 ; RUN:   | FileCheck %s
 
@@ skipping 247 matching lines @@
   ret i64 %a
 }
 ; CHECK-LABEL: test_atomic_rmw_add_64_global
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
 declare void @use_ptr(i32 %iptr)
 
 define i64 @test_atomic_rmw_add_64_alloca(i32 %iptr, i64 %v) {
 entry:
+  br label %eblock  ; Disable alloca optimization
+eblock:
   %alloca_ptr = alloca i8, i32 16, align 16
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.rmw.i64(i32 1, i64* %ptr, i64 %v, i32 6)
   store i8 0, i8* %alloca_ptr, align 1
   store i8 1, i8* %alloca_ptr, align 1
   store i8 2, i8* %alloca_ptr, align 1
   store i8 3, i8* %alloca_ptr, align 1
   %__5 = ptrtoint i8* %alloca_ptr to i32
   call void @use_ptr(i32 %__5)
   ret i64 %old
@@ skipping 520 matching lines @@
 ; CHECK-DAG: mov ecx
 ; CHECK-DAG: mov ebx
 ; CHECK: lock cmpxchg8b QWORD PTR [e{{.[^x]}}
 ; CHECK-DAG: mov {{.*}},edx
 ; CHECK-DAG: mov {{.*}},eax
 
 ; Test with some more register pressure. When we have an alloca, ebp is
 ; used to manage the stack frame, so it cannot be used as a register either.
 define i64 @test_atomic_cmpxchg_64_alloca(i32 %iptr, i64 %expected, i64 %desired) {
 entry:
+  br label %eblock  ; Disable alloca optimization
+eblock:
   %alloca_ptr = alloca i8, i32 16, align 16
   %ptr = inttoptr i32 %iptr to i64*
   %old = call i64 @llvm.nacl.atomic.cmpxchg.i64(i64* %ptr, i64 %expected,
                                                 i64 %desired, i32 6, i32 6)
   store i8 0, i8* %alloca_ptr, align 1
   store i8 1, i8* %alloca_ptr, align 1
   store i8 2, i8* %alloca_ptr, align 1
   store i8 3, i8* %alloca_ptr, align 1
   %__6 = ptrtoint i8* %alloca_ptr to i32
   call void @use_ptr(i32 %__6)
@@ skipping 194 matching lines @@
   br i1 %cmp, label %done, label %body
 done:
   ret void
 }
 ; O2-LABEL: test_cmpxchg8b_regalloc
 ;;; eax and some other register will be used in the cmpxchg instruction.
 ; O2: lock cmpxchg8b QWORD PTR
 ;;; Make sure eax/ecx/edx/ebx aren't used again, e.g. as the induction variable.
 ; O2-NOT: {{eax|ecx|edx|ebx}}
 ; O2: pop ebx