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Side by Side Diff: src/IceTargetLoweringX8664.cpp

Issue 1361803002: Subzero: Improve handling of alloca instructions of constant size. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Add a couple of basic tests Created 5 years, 3 months ago
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1 //===- subzero/src/IceTargetLoweringX8664.cpp - x86-64 lowering -----------===// 1 //===- subzero/src/IceTargetLoweringX8664.cpp - x86-64 lowering -----------===//
2 // 2 //
3 // The Subzero Code Generator 3 // The Subzero Code Generator
4 // 4 //
5 // This file is distributed under the University of Illinois Open Source 5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details. 6 // License. See LICENSE.TXT for details.
7 // 7 //
8 //===----------------------------------------------------------------------===// 8 //===----------------------------------------------------------------------===//
9 /// 9 ///
10 /// \file 10 /// \file
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505 Traits::X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes; 505 Traits::X86_RET_IP_SIZE_BYTES + PreservedRegsSizeBytes;
506 uint32_t StackSize = 506 uint32_t StackSize =
507 Traits::applyStackAlignment(StackOffset + SpillAreaSizeBytes); 507 Traits::applyStackAlignment(StackOffset + SpillAreaSizeBytes);
508 SpillAreaSizeBytes = StackSize - StackOffset; 508 SpillAreaSizeBytes = StackSize - StackOffset;
509 } 509 }
510 510
511 // Generate "sub esp, SpillAreaSizeBytes" 511 // Generate "sub esp, SpillAreaSizeBytes"
512 if (SpillAreaSizeBytes) 512 if (SpillAreaSizeBytes)
513 _sub(getPhysicalRegister(Traits::RegisterSet::Reg_esp), 513 _sub(getPhysicalRegister(Traits::RegisterSet::Reg_esp),
514 Ctx->getConstantInt32(SpillAreaSizeBytes)); 514 Ctx->getConstantInt32(SpillAreaSizeBytes));
515
516 // Account for alloca instructions with known frame offsets.
517 SpillAreaSizeBytes += FixedAllocaSizeBytes;
518
515 Ctx->statsUpdateFrameBytes(SpillAreaSizeBytes); 519 Ctx->statsUpdateFrameBytes(SpillAreaSizeBytes);
516 520
521 // Initialize the stack adjustment so that after all the known-frame-offset
522 // alloca instructions are emitted, the stack adjustment will reach zero.
517 resetStackAdjustment(); 523 resetStackAdjustment();
524 updateStackAdjustment(-FixedAllocaSizeBytes);
518 525
519 // Fill in stack offsets for stack args, and copy args into registers for 526 // Fill in stack offsets for stack args, and copy args into registers for
520 // those that were register-allocated. Args are pushed right to left, so 527 // those that were register-allocated. Args are pushed right to left, so
521 // Arg[0] is closest to the stack/frame pointer. 528 // Arg[0] is closest to the stack/frame pointer.
522 Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg()); 529 Variable *FramePtr = getPhysicalRegister(getFrameOrStackReg());
523 size_t BasicFrameOffset = 530 size_t BasicFrameOffset =
524 PreservedRegsSizeBytes + Traits::X86_RET_IP_SIZE_BYTES; 531 PreservedRegsSizeBytes + Traits::X86_RET_IP_SIZE_BYTES;
525 if (!IsEbpBasedFrame) 532 if (!IsEbpBasedFrame)
526 BasicFrameOffset += SpillAreaSizeBytes; 533 BasicFrameOffset += SpillAreaSizeBytes;
527 534
528 const VarList &Args = Func->getArgs(); 535 const VarList &Args = Func->getArgs();
529 size_t InArgsSizeBytes = 0; 536 size_t InArgsSizeBytes = 0;
530 unsigned NumXmmArgs = 0; 537 unsigned NumXmmArgs = 0;
531 unsigned NumGPRArgs = 0; 538 unsigned NumGPRArgs = 0;
532 for (Variable *Arg : Args) { 539 for (Variable *Arg : Args) {
533 // Skip arguments passed in registers. 540 // Skip arguments passed in registers.
534 if (isVectorType(Arg->getType()) || isScalarFloatingType(Arg->getType())) { 541 if (isVectorType(Arg->getType()) || isScalarFloatingType(Arg->getType())) {
535 if (NumXmmArgs < Traits::X86_MAX_XMM_ARGS) { 542 if (NumXmmArgs < Traits::X86_MAX_XMM_ARGS) {
536 ++NumXmmArgs; 543 ++NumXmmArgs;
537 continue; 544 continue;
538 } 545 }
539 } else { 546 } else {
540 assert(isScalarIntegerType(Arg->getType())); 547 assert(isScalarIntegerType(Arg->getType()));
541 if (NumGPRArgs < Traits::X86_MAX_GPR_ARGS) { 548 if (NumGPRArgs < Traits::X86_MAX_GPR_ARGS) {
542 ++NumGPRArgs; 549 ++NumGPRArgs;
543 continue; 550 continue;
544 } 551 }
545 } 552 }
546 finishArgumentLowering(Arg, FramePtr, BasicFrameOffset, InArgsSizeBytes); 553 // For esp-based frames, the esp value may not stabilize to its home value
554 // until after all the fixed-size alloca instructions have executed. In
555 // this case, a stack adjustment is needed when accessing in-args in order
556 // to copy them into registers.
557 size_t StackAdjBytes = IsEbpBasedFrame ? 0 : -FixedAllocaSizeBytes;
558 finishArgumentLowering(Arg, FramePtr, BasicFrameOffset, StackAdjBytes,
559 InArgsSizeBytes);
547 } 560 }
548 561
549 // Fill in stack offsets for locals. 562 // Fill in stack offsets for locals.
550 assignVarStackSlots(SortedSpilledVariables, SpillAreaPaddingBytes, 563 assignVarStackSlots(SortedSpilledVariables, SpillAreaPaddingBytes,
551 SpillAreaSizeBytes, GlobalsAndSubsequentPaddingSize, 564 SpillAreaSizeBytes, GlobalsAndSubsequentPaddingSize,
552 IsEbpBasedFrame); 565 IsEbpBasedFrame);
553 // Assign stack offsets to variables that have been linked to spilled 566 // Assign stack offsets to variables that have been linked to spilled
554 // variables. 567 // variables.
555 for (Variable *Var : VariablesLinkedToSpillSlots) { 568 for (Variable *Var : VariablesLinkedToSpillSlots) {
556 Variable *Linked = 569 Variable *Linked =
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944 // case the high-level table has extra entries. 957 // case the high-level table has extra entries.
945 #define X(tag, sizeLog2, align, elts, elty, str) \ 958 #define X(tag, sizeLog2, align, elts, elty, str) \
946 static_assert(_table1_##tag == _table2_##tag, \ 959 static_assert(_table1_##tag == _table2_##tag, \
947 "Inconsistency between ICETYPEX8664_TABLE and ICETYPE_TABLE"); 960 "Inconsistency between ICETYPEX8664_TABLE and ICETYPE_TABLE");
948 ICETYPE_TABLE 961 ICETYPE_TABLE
949 #undef X 962 #undef X
950 } // end of namespace dummy3 963 } // end of namespace dummy3
951 } // end of anonymous namespace 964 } // end of anonymous namespace
952 965
953 } // end of namespace Ice 966 } // end of namespace Ice
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