MIPS: [turbofan] Call ArgumentsAccessStub to materialize arguments.

MIPS: [turbofan] Call ArgumentsAccessStub to materialize arguments.

Port of https://codereview.chromium.org/1348773002/

BUG=

[paul.l..., 2015-09-24 04:07:04]

paul.lind@imgtec.com changed reviewers:
+ paul.lind@imgtec.com

[paul.l..., 2015-09-24 04:07:05]

https://codereview.chromium.org/1361143005/diff/1/src/mips/code-stubs-mips.cc
File src/mips/code-stubs-mips.cc (right):

https://codereview.chromium.org/1361143005/diff/1/src/mips/code-stubs-mips.cc...
src/mips/code-stubs-mips.cc:1695: __ Branch(&skip2_eq, eq, a1,
Operand(zero_reg));
The main bug is this a1 should have been changed to t2. However, we both fixed
some other issues. I will upload a new CL

[paul.l..., 2015-09-24 04:33:58]

https://codereview.chromium.org/1361143005/diff/1/src/mips/code-stubs-mips.cc
File src/mips/code-stubs-mips.cc (right):

https://codereview.chromium.org/1361143005/diff/1/src/mips/code-stubs-mips.cc...
src/mips/code-stubs-mips.cc:1695: __ Branch(&skip2_eq, eq, a1,
Operand(zero_reg));
The 2 branches here (in older code also) bugged me, and I wrote this:
 // v0 = address of new object(s) (tagged)
  // a2 = argument count (smi-tagged)
  // t5 = scratch.
  // Get the arguments boilerplate from the current native context into t0.
  const int kNormalOffset =
      Context::SlotOffset(Context::SLOPPY_ARGUMENTS_MAP_INDEX);
  const int kAliasedOffset =
      Context::SlotOffset(Context::FAST_ALIASED_ARGUMENTS_MAP_INDEX);

  __ lw(t0, MemOperand(cp, Context::SlotOffset(Context::GLOBAL_OBJECT_INDEX)));
  __ lw(t0, FieldMemOperand(t0, GlobalObject::kNativeContextOffset));
  Label load_normal;
  __ Branch(USE_DELAY_SLOT, &load_normal, eq, t2, Operand(zero_reg));
  __ lw(t5, MemOperand(t0, kNormalOffset));
  __ lw(t5, MemOperand(t0, kAliasedOffset));
  __ bind(&load_normal):
  __ mov(t0, t5);

But that shortens code from 6 instructions (with 2 nops, and one memory
reference) to 4 instrucions and two memory references. And looking at these
offsets, I don't think they'd share same cacheline, so what I wrote look nice
but is almost certainly worse than two branches. So never mind :-)