Index: test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc |
diff --git a/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc b/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc |
index 71c2d44d2f51722fe2bf6fec1dd2a5f7390006ec..dd48ab98c60ad4f9f23a894d1e81ee2e73bae5b3 100644 |
--- a/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc |
+++ b/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc |
@@ -3035,6 +3035,199 @@ TEST_F(InstructionSelectorTest, Float64SubWithMinusZero) { |
EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
} |
+ |
+TEST_F(InstructionSelectorTest, Float32Max) { |
+ StreamBuilder m(this, kMachFloat32, kMachFloat32, kMachFloat32); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const n = m.Float32Max(p0, p1); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ // Float32Max is `(b < a) ? a : b`. |
+ ASSERT_EQ(1U, s.size()); |
+ EXPECT_EQ(kArm64Float32CmpAndFloat32Sel, s[0]->arch_opcode()); |
+ EXPECT_EQ(kFlags_select, s[0]->flags_mode()); |
+ EXPECT_EQ(kUnsignedLessThan, s[0]->flags_condition()); |
+ ASSERT_EQ(4U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(2))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(3))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+} |
+ |
+ |
+TEST_F(InstructionSelectorTest, Float32Min) { |
+ StreamBuilder m(this, kMachFloat32, kMachFloat32, kMachFloat32); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const n = m.Float32Min(p0, p1); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ // Float32Min is `(a < b) ? a : b`. |
+ ASSERT_EQ(1U, s.size()); |
+ EXPECT_EQ(kArm64Float32CmpAndFloat32Sel, s[0]->arch_opcode()); |
+ EXPECT_EQ(kFlags_select, s[0]->flags_mode()); |
+ EXPECT_EQ(kUnsignedLessThan, s[0]->flags_condition()); |
+ ASSERT_EQ(4U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(2))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(3))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+} |
+ |
+ |
+TEST_F(InstructionSelectorTest, Float32MaxZeroOnLeft) { |
+ float zeroes[] = {0.0f, -0.0f}; |
+ TRACED_FOREACH(float, zero, zeroes) { |
+ StreamBuilder m(this, kMachFloat32, kMachFloat32); |
+ Node* const p0 = m.Float32Constant(zero); |
+ Node* const p1 = m.Parameter(0); |
+ Node* const n = m.Float32Max(p0, p1); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ // Float32Max(a = 0.0f, b) is `(b < 0.0f) ? a : b`. |
+ ASSERT_EQ(1U, s.size()); |
+ EXPECT_EQ(kArm64Float32CmpAndFloat32Sel, s[0]->arch_opcode()); |
+ EXPECT_EQ(kFlags_select, s[0]->flags_mode()); |
+ EXPECT_EQ(kUnsignedLessThan, s[0]->flags_condition()); |
+ ASSERT_EQ(4U, s[0]->InputCount()); |
+ EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate()); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(0.0f, s.ToFloat32(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(2))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(3))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ } |
+} |
+ |
+ |
+TEST_F(InstructionSelectorTest, Float32MinZeroOnRight) { |
+ float zeroes[] = {0.0f, -0.0f}; |
+ TRACED_FOREACH(float, zero, zeroes) { |
+ StreamBuilder m(this, kMachFloat32, kMachFloat32); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Float32Constant(zero); |
+ Node* const n = m.Float32Min(p0, p1); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ // Float32Min(a, b = 0.0f) is `(a < 0.0f) ? a : b`. |
+ ASSERT_EQ(1U, s.size()); |
+ EXPECT_EQ(kArm64Float32CmpAndFloat32Sel, s[0]->arch_opcode()); |
+ EXPECT_EQ(kFlags_select, s[0]->flags_mode()); |
+ EXPECT_EQ(kUnsignedLessThan, s[0]->flags_condition()); |
+ ASSERT_EQ(4U, s[0]->InputCount()); |
+ EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate()); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(0.0f, s.ToFloat32(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(2))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(3))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ } |
+} |
+ |
+ |
+TEST_F(InstructionSelectorTest, Float64Max) { |
+ StreamBuilder m(this, kMachFloat64, kMachFloat64, kMachFloat64); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const n = m.Float64Max(p0, p1); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ // Float64Max is `(b < a) ? a : b`. |
+ ASSERT_EQ(1U, s.size()); |
+ EXPECT_EQ(kArm64Float64CmpAndFloat64Sel, s[0]->arch_opcode()); |
+ EXPECT_EQ(kFlags_select, s[0]->flags_mode()); |
+ EXPECT_EQ(kUnsignedLessThan, s[0]->flags_condition()); |
+ ASSERT_EQ(4U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(2))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(3))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+} |
+ |
+ |
+TEST_F(InstructionSelectorTest, Float64Min) { |
+ StreamBuilder m(this, kMachFloat64, kMachFloat64, kMachFloat64); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Parameter(1); |
+ Node* const n = m.Float64Min(p0, p1); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ // Float64Min is `(a < b) ? a : b`. |
+ ASSERT_EQ(1U, s.size()); |
+ EXPECT_EQ(kArm64Float64CmpAndFloat64Sel, s[0]->arch_opcode()); |
+ EXPECT_EQ(kFlags_select, s[0]->flags_mode()); |
+ EXPECT_EQ(kUnsignedLessThan, s[0]->flags_condition()); |
+ ASSERT_EQ(4U, s[0]->InputCount()); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(2))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(3))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+} |
+ |
+ |
+TEST_F(InstructionSelectorTest, Float64MaxZeroOnLeft) { |
+ double zeroes[] = {0.0, -0.0}; |
+ TRACED_FOREACH(double, zero, zeroes) { |
+ StreamBuilder m(this, kMachFloat64, kMachFloat64); |
+ Node* const p0 = m.Float64Constant(zero); |
+ Node* const p1 = m.Parameter(0); |
+ Node* const n = m.Float64Max(p0, p1); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ // Float64Max(a = 0.0, b) is `(b < 0.0) ? a : b`. |
+ ASSERT_EQ(1U, s.size()); |
+ EXPECT_EQ(kArm64Float64CmpAndFloat64Sel, s[0]->arch_opcode()); |
+ EXPECT_EQ(kFlags_select, s[0]->flags_mode()); |
+ EXPECT_EQ(kUnsignedLessThan, s[0]->flags_condition()); |
+ ASSERT_EQ(4U, s[0]->InputCount()); |
+ EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate()); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(0.0, s.ToFloat64(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(2))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(3))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ } |
+} |
+ |
+ |
+TEST_F(InstructionSelectorTest, Float64MinZeroOnRight) { |
+ double zeroes[] = {0.0, -0.0}; |
+ TRACED_FOREACH(double, zero, zeroes) { |
+ StreamBuilder m(this, kMachFloat64, kMachFloat64); |
+ Node* const p0 = m.Parameter(0); |
+ Node* const p1 = m.Float64Constant(zero); |
+ Node* const n = m.Float64Min(p0, p1); |
+ m.Return(n); |
+ Stream s = m.Build(); |
+ // Float64Min(a, b = 0.0) is `(a < 0.0) ? a : b`. |
+ ASSERT_EQ(1U, s.size()); |
+ EXPECT_EQ(kArm64Float64CmpAndFloat64Sel, s[0]->arch_opcode()); |
+ EXPECT_EQ(kFlags_select, s[0]->flags_mode()); |
+ EXPECT_EQ(kUnsignedLessThan, s[0]->flags_condition()); |
+ ASSERT_EQ(4U, s[0]->InputCount()); |
+ EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate()); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0))); |
+ EXPECT_EQ(0.0, s.ToFloat64(s[0]->InputAt(1))); |
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(2))); |
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(3))); |
+ ASSERT_EQ(1U, s[0]->OutputCount()); |
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output())); |
+ } |
+} |
+ |
+ |
} // namespace compiler |
} // namespace internal |
} // namespace v8 |