[arm64] Implement Float(32|64)(Min|Max) using fcsel.

src/compiler/arm64/instruction-selector-arm64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/instruction-selector-impl.h"
 #include "src/compiler/node-matchers.h"
 #include "src/compiler/node-properties.h"
 
 namespace v8 {
 namespace internal {
@@ skipping 1325 matching lines @@
 
 
 void InstructionSelector::VisitFloat64Mod(Node* node) {
   Arm64OperandGenerator g(this);
   Emit(kArm64Float64Mod, g.DefineAsFixed(node, d0),
        g.UseFixed(node->InputAt(0), d0),
        g.UseFixed(node->InputAt(1), d1))->MarkAsCall();
 }
 
 
-void InstructionSelector::VisitFloat32Max(Node* node) { UNREACHABLE(); }
-
-
-void InstructionSelector::VisitFloat64Max(Node* node) { UNREACHABLE(); }
-
-
-void InstructionSelector::VisitFloat32Min(Node* node) { UNREACHABLE(); }
-
-
-void InstructionSelector::VisitFloat64Min(Node* node) { UNREACHABLE(); }
-
-
 void InstructionSelector::VisitFloat32Abs(Node* node) {
   VisitRR(this, kArm64Float32Abs, node);
 }
 
 
 void InstructionSelector::VisitFloat64Abs(Node* node) {
   VisitRR(this, kArm64Float64Abs, node);
 }
 
 
@@ skipping 226 matching lines @@
   if (cont->IsBranch()) {
     selector->Emit(opcode, g.NoOutput(), left, right,
                    g.Label(cont->true_block()), g.Label(cont->false_block()));
   } else {
     DCHECK(cont->IsSet());
     selector->Emit(opcode, g.DefineAsRegister(cont->result()), left, right);
   }
 }
 
 
+// Shared routine for multiple compare-and-select operations.
+void VisitCompareAndSelect(InstructionSelector* selector,
+                           InstructionCode opcode, InstructionOperand cmp_left,
+                           InstructionOperand cmp_right,
+                           InstructionOperand if_true,
+                           InstructionOperand if_false,
+                           FlagsContinuation* cont) {
+  Arm64OperandGenerator g(selector);
+  opcode = cont->Encode(opcode);
+  DCHECK(cont->IsSelect());
+  selector->Emit(opcode, g.DefineAsRegister(cont->result()), cmp_left,
+                 cmp_right, if_true, if_false);
+}
+
+
 // Shared routine for multiple word compare operations.
 void VisitWordCompare(InstructionSelector* selector, Node* node,
                       InstructionCode opcode, FlagsContinuation* cont,
                       bool commutative, ImmediateMode immediate_mode) {
   Arm64OperandGenerator g(selector);
   Node* left = node->InputAt(0);
   Node* right = node->InputAt(1);
 
   // Match immediates on left or right side of comparison.
   if (g.CanBeImmediate(right, immediate_mode)) {
@@ skipping 30 matching lines @@
   VisitWordTest(selector, node, kArm64Tst32, cont);
 }
 
 
 void VisitWord64Test(InstructionSelector* selector, Node* node,
                      FlagsContinuation* cont) {
   VisitWordTest(selector, node, kArm64Tst, cont);
 }
 
 
-// Shared routine for multiple float64 compare operations.
+// Shared routine for multiple float32 compare operations.
 void VisitFloat32Compare(InstructionSelector* selector, Node* node,
                          FlagsContinuation* cont) {
   Arm64OperandGenerator g(selector);
   Float32BinopMatcher m(node);
   if (m.right().Is(0.0f)) {
     VisitCompare(selector, kArm64Float32Cmp, g.UseRegister(m.left().node()),
                  g.UseImmediate(m.right().node()), cont);
   } else {
     VisitCompare(selector, kArm64Float32Cmp, g.UseRegister(m.left().node()),
                  g.UseRegister(m.right().node()), cont);
   }
 }
 
 
+void VisitFloat32CompareAndSelect(InstructionSelector* selector, Node* node,
+                                  InstructionCode opcode, Node* cmp_left,
+                                  Node* cmp_right, Node* sel_true,
+                                  Node* sel_false, FlagsContinuation* cont) {
+  // (cmp_left <op> cmp_right) ? sel_true : sel_false
+  Arm64OperandGenerator g(selector);
+  if (Float32Matcher(cmp_right).Is(0.0f)) {
+    VisitCompareAndSelect(selector, opcode, g.UseRegister(cmp_left),
+                          g.UseImmediate(cmp_right), g.UseRegister(sel_true),
+                          g.UseRegister(sel_false), cont);
+  } else {
+    VisitCompareAndSelect(selector, opcode, g.UseRegister(cmp_left),
+                          g.UseRegister(cmp_right), g.UseRegister(sel_true),
+                          g.UseRegister(sel_false), cont);
+  }
+}
+
+
 // Shared routine for multiple float64 compare operations.
 void VisitFloat64Compare(InstructionSelector* selector, Node* node,
                          FlagsContinuation* cont) {
   Arm64OperandGenerator g(selector);
   Float64BinopMatcher m(node);
   if (m.right().Is(0.0)) {
     VisitCompare(selector, kArm64Float64Cmp, g.UseRegister(m.left().node()),
                  g.UseImmediate(m.right().node()), cont);
   } else {
     VisitCompare(selector, kArm64Float64Cmp, g.UseRegister(m.left().node()),
                  g.UseRegister(m.right().node()), cont);
   }
 }
 
+
+void VisitFloat64CompareAndSelect(InstructionSelector* selector, Node* node,
+                                  InstructionCode opcode, Node* cmp_left,
+                                  Node* cmp_right, Node* sel_true,
+                                  Node* sel_false, FlagsContinuation* cont) {
+  // (cmp_left <op> cmp_right) ? sel_true : sel_false
+  Arm64OperandGenerator g(selector);
+  if (Float64Matcher(cmp_right).Is(0.0)) {
+    VisitCompareAndSelect(selector, opcode, g.UseRegister(cmp_left),
+                          g.UseImmediate(cmp_right), g.UseRegister(sel_true),
+                          g.UseRegister(sel_false), cont);
+  } else {
+    VisitCompareAndSelect(selector, opcode, g.UseRegister(cmp_left),
+                          g.UseRegister(cmp_right), g.UseRegister(sel_true),
+                          g.UseRegister(sel_false), cont);
+  }
+}
+
 }  // namespace
 
 
 void InstructionSelector::VisitBranch(Node* branch, BasicBlock* tbranch,
                                       BasicBlock* fbranch) {
   OperandGenerator g(this);
   Node* user = branch;
   Node* value = branch->InputAt(0);
 
   FlagsContinuation cont(kNotEqual, tbranch, fbranch);
@@ skipping 327 matching lines @@
   VisitFloat64Compare(this, node, &cont);
 }
 
 
 void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) {
   FlagsContinuation cont(kUnsignedLessThanOrEqual, node);
   VisitFloat64Compare(this, node, &cont);
 }
 
 
+void InstructionSelector::VisitFloat32Max(Node* node) {
+  // (b < a) ? a : b
+  FlagsContinuation cont(kUnsignedLessThan, node, kFlags_select);
+  VisitFloat32CompareAndSelect(this, node, kArm64Float32CmpAndFloat32Sel,
+                               node->InputAt(1), node->InputAt(0),
+                               node->InputAt(0), node->InputAt(1), &cont);
+}
+
+
+void InstructionSelector::VisitFloat32Min(Node* node) {
+  // (a < b) ? a : b
+  FlagsContinuation cont(kUnsignedLessThan, node, kFlags_select);
+  VisitFloat32CompareAndSelect(this, node, kArm64Float32CmpAndFloat32Sel,
+                               node->InputAt(0), node->InputAt(1),
+                               node->InputAt(0), node->InputAt(1), &cont);
+}
+
+
+void InstructionSelector::VisitFloat64Max(Node* node) {
+  // (b < a) ? a : b
+  FlagsContinuation cont(kUnsignedLessThan, node, kFlags_select);
+  VisitFloat64CompareAndSelect(this, node, kArm64Float64CmpAndFloat64Sel,
+                               node->InputAt(1), node->InputAt(0),
+                               node->InputAt(0), node->InputAt(1), &cont);
+}
+
+
+void InstructionSelector::VisitFloat64Min(Node* node) {
+  // (a < b) ? a : b
+  FlagsContinuation cont(kUnsignedLessThan, node, kFlags_select);
+  VisitFloat64CompareAndSelect(this, node, kArm64Float64CmpAndFloat64Sel,
+                               node->InputAt(0), node->InputAt(1),
+                               node->InputAt(0), node->InputAt(1), &cont);
+}
+
+
 void InstructionSelector::VisitFloat64ExtractLowWord32(Node* node) {
   Arm64OperandGenerator g(this);
   Emit(kArm64Float64ExtractLowWord32, g.DefineAsRegister(node),
        g.UseRegister(node->InputAt(0)));
 }
 
 
 void InstructionSelector::VisitFloat64ExtractHighWord32(Node* node) {
   Arm64OperandGenerator g(this);
   Emit(kArm64Float64ExtractHighWord32, g.DefineAsRegister(node),
@@ skipping 32 matching lines @@
     return;
   }
   Emit(kArm64Float64InsertHighWord32, g.DefineAsRegister(node),
        g.UseRegister(left), g.UseRegister(right));
 }
 
 
 // static
 MachineOperatorBuilder::Flags
 InstructionSelector::SupportedMachineOperatorFlags() {
-  return MachineOperatorBuilder::kFloat64RoundDown |
+  return MachineOperatorBuilder::kFloat32Max |
+         MachineOperatorBuilder::kFloat32Min |
+         MachineOperatorBuilder::kFloat64Max |
+         MachineOperatorBuilder::kFloat64Min |
+         MachineOperatorBuilder::kFloat64RoundDown |
          MachineOperatorBuilder::kFloat64RoundTruncate |
          MachineOperatorBuilder::kFloat64RoundTiesAway |
          MachineOperatorBuilder::kWord32ShiftIsSafe |
          MachineOperatorBuilder::kInt32DivIsSafe |
          MachineOperatorBuilder::kUint32DivIsSafe;
 }
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8