[arm64] Implement Float(32|64)(Min|Max) using fcsel.

src/compiler/arm64/code-generator-arm64.cc

 // Copyright 2014 the V8 project authors. All rights reserved.
 // Use of this source code is governed by a BSD-style license that can be
 // found in the LICENSE file.
 
 #include "src/compiler/code-generator.h"
 
 #include "src/arm64/frames-arm64.h"
 #include "src/arm64/macro-assembler-arm64.h"
 #include "src/compiler/code-generator-impl.h"
 #include "src/compiler/gap-resolver.h"
@@ skipping 367 matching lines @@
   if (descriptor->IsJSFunctionCall() || stack_slots > 0) {
     __ Mov(jssp, fp);
     __ Pop(fp, lr);
   }
 }
 
 
 // Assembles an instruction after register allocation, producing machine code.
 void CodeGenerator::AssembleArchInstruction(Instruction* instr) {
   Arm64OperandConverter i(this, instr);
-  InstructionCode opcode = instr->opcode();
-  switch (ArchOpcodeField::decode(opcode)) {
+  switch (instr->arch_opcode()) {
     case kArchCallCodeObject: {
       EnsureSpaceForLazyDeopt();
       if (instr->InputAt(0)->IsImmediate()) {
         __ Call(Handle<Code>::cast(i.InputHeapObject(0)),
                 RelocInfo::CODE_TARGET);
       } else {
         Register target = i.InputRegister(0);
         __ Add(target, target, Code::kHeaderSize - kHeapObjectTag);
         __ Call(target);
       }
@@ skipping 99 matching lines @@
     case kArm64Float64RoundTruncate:
       __ Frintz(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
       break;
     case kArm64Float64RoundUp:
       __ Frintp(i.OutputDoubleRegister(), i.InputDoubleRegister(0));
       break;
     case kArm64Add:
       __ Add(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1));
       break;
     case kArm64Add32:
-      if (FlagsModeField::decode(opcode) != kFlags_none) {
+      if (instr->flags_mode() != kFlags_none) {
         __ Adds(i.OutputRegister32(), i.InputRegister32(0),
                 i.InputOperand2_32(1));
       } else {
         __ Add(i.OutputRegister32(), i.InputRegister32(0),
                i.InputOperand2_32(1));
       }
       break;
     case kArm64And:
       __ And(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1));
       break;
@@ skipping 115 matching lines @@
     case kArm64Eon:
       __ Eon(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1));
       break;
     case kArm64Eon32:
       __ Eon(i.OutputRegister32(), i.InputRegister32(0), i.InputOperand2_32(1));
       break;
     case kArm64Sub:
       __ Sub(i.OutputRegister(), i.InputRegister(0), i.InputOperand2_64(1));
       break;
     case kArm64Sub32:
-      if (FlagsModeField::decode(opcode) != kFlags_none) {
+      if (instr->flags_mode() != kFlags_none) {
         __ Subs(i.OutputRegister32(), i.InputRegister32(0),
                 i.InputOperand2_32(1));
       } else {
         __ Sub(i.OutputRegister32(), i.InputRegister32(0),
                i.InputOperand2_32(1));
       }
       break;
     case kArm64Lsl:
       ASSEMBLE_SHIFT(Lsl, 64);
       break;
@@ skipping 85 matching lines @@
       break;
     case kArm64Cmn32:
       __ Cmn(i.InputRegister32(0), i.InputOperand32(1));
       break;
     case kArm64Tst:
       __ Tst(i.InputRegister(0), i.InputOperand(1));
       break;
     case kArm64Tst32:
       __ Tst(i.InputRegister32(0), i.InputOperand32(1));
       break;
+    case kArm64Float32CmpAndFloat32Sel:

[Benedikt Meurer, 2015/09/21 17:31:43]

Hm, this instruction looks redundant. Why do you need it?

[jbramley, 2015/09/22 07:45:20]

Because, although I haven't done so yet, we might want the type of the select
arguments to differ from the type of the comparison. Encoding that in the
architecture-specific part of the opcode seemed the most sensible thing to do.

+      DCHECK(instr->flags_mode() == kFlags_select);
+    // Fall through.
     case kArm64Float32Cmp:
       if (instr->InputAt(1)->IsDoubleRegister()) {
         __ Fcmp(i.InputFloat32Register(0), i.InputFloat32Register(1));
       } else {
         DCHECK(instr->InputAt(1)->IsImmediate());
         // 0.0 is the only immediate supported by fcmp instructions.
         DCHECK(i.InputDouble(1) == 0.0);
         __ Fcmp(i.InputFloat32Register(0), i.InputDouble(1));
       }
       break;
@@ skipping 20 matching lines @@
     case kArm64Float32Min:
       __ Fmin(i.OutputFloat32Register(), i.InputFloat32Register(0),
               i.InputFloat32Register(1));
       break;
     case kArm64Float32Abs:
       __ Fabs(i.OutputFloat32Register(), i.InputFloat32Register(0));
       break;
     case kArm64Float32Sqrt:
       __ Fsqrt(i.OutputFloat32Register(), i.InputFloat32Register(0));
       break;
+    case kArm64Float64CmpAndFloat64Sel:

[Benedikt Meurer, 2015/09/21 17:31:43]

Same here?

+      DCHECK(instr->flags_mode() == kFlags_select);
+    // Fall through.
     case kArm64Float64Cmp:
       if (instr->InputAt(1)->IsDoubleRegister()) {
         __ Fcmp(i.InputDoubleRegister(0), i.InputDoubleRegister(1));
       } else {
         DCHECK(instr->InputAt(1)->IsImmediate());
         // 0.0 is the only immediate supported by fcmp instructions.
         DCHECK(i.InputDouble(1) == 0.0);
         __ Fcmp(i.InputDoubleRegister(0), i.InputDouble(1));
       }
       break;
@@ skipping 261 matching lines @@
 
   // Materialize a full 64-bit 1 or 0 value. The result register is always the
   // last output of the instruction.
   DCHECK_NE(0u, instr->OutputCount());
   Register reg = i.OutputRegister(instr->OutputCount() - 1);
   Condition cc = FlagsConditionToCondition(condition);
   __ Cset(reg, cc);
 }
 
 
+void CodeGenerator::AssembleArchSelect(Instruction* instr,
+                                       FlagsCondition condition) {
+  Arm64OperandConverter i(this, instr);
+
+  DCHECK_EQ(1u, instr->OutputCount());
+
+  Condition cc = FlagsConditionToCondition(condition);
+  switch (instr->arch_opcode()) {
+    case kArm64Float32CmpAndFloat32Sel: {

[Benedikt Meurer, 2015/09/21 17:31:43]

I'm not sure if this approach scales well. Because the select is actually
independent of the comparison, the operands of the comparison, conceptionally.
Did you consider using different kinds of Select, i.e. SelectFloat32,
SelectFloat64 and so on?

[jbramley, 2015/09/22 07:45:21]

Indeed, but (unless I'm mistaken), TF can't track flags dependencies between
instructions. In all other cases, instructions that produce flags always consume
them (either explicitly or using a FlagsContinuation).

Is there a better way to handle that?

+      DoubleRegister result = i.OutputFloat32Register();
+      DoubleRegister a = i.InputFloat32Register(instr->InputCount() - 2);
+      DoubleRegister b = i.InputFloat32Register(instr->InputCount() - 1);
+      __ Fcsel(result, a, b, cc);
+      return;
+    }
+    case kArm64Float64CmpAndFloat64Sel: {
+      DoubleRegister result = i.OutputFloat64Register();
+      DoubleRegister a = i.InputFloat64Register(instr->InputCount() - 2);
+      DoubleRegister b = i.InputFloat64Register(instr->InputCount() - 1);
+      __ Fcsel(result, a, b, cc);
+      return;
+    }
+    default:
+      UNREACHABLE();
+      return;
+  }
+}
+
+
 void CodeGenerator::AssembleArchLookupSwitch(Instruction* instr) {
   Arm64OperandConverter i(this, instr);
   Register input = i.InputRegister32(0);
   for (size_t index = 2; index < instr->InputCount(); index += 2) {
     __ Cmp(input, i.InputInt32(index + 0));
     __ B(eq, GetLabel(i.InputRpo(index + 1)));
   }
   AssembleArchJump(i.InputRpo(1));
 }
 
@@ skipping 318 matching lines @@
       padding_size -= kInstructionSize;
     }
   }
 }
 
 #undef __
 
 }  // namespace compiler
 }  // namespace internal
 }  // namespace v8