Subzero. Enables (most) crosstests for ARM32.

tests_lit/llvm2ice_tests/fp.convert.ll

 ; This tries to be a comprehensive test of f32 and f64 convert operations.
 ; The CHECK lines are only checking for basic instruction patterns
 ; that should be present regardless of the optimization level, so
 ; there are no special OPTM1 match lines.
 
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
 
 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
 ; RUN:   --target arm32 -i %s --args -O2 --skip-unimplemented \
@@ skipping 81 matching lines @@
 define internal i32 @doubleToSigned32Const() {
 entry:
   %conv = fptosi double 867.5309 to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: doubleToSigned32Const
 ; CHECK: cvttsd2si
 ; ARM32-LABEL: doubleToSigned32Const
 ; ARM32-DAG: movw [[ADDR:r[0-9]+]], #:lower16:.L$
 ; ARM32-DAG: movt [[ADDR]], #:upper16:.L$
-; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]], #0{{\]}}
+; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}}
 ; ARM32-DAG: vcvt.s32.f64 [[REG:s[0-9]+]], [[DREG]]
 ; ARM32-DAF: vmov {{r[0-9]+}}, [[REG]]
 
 define internal i32 @floatToSigned32(float %a) {
 entry:
   %conv = fptosi float %a to i32
   ret i32 %conv
 }
 ; CHECK-LABEL: floatToSigned32
 ; CHECK: cvttss2si
@@ skipping 475 matching lines @@
   %conv = bitcast i64 9035768 to double
   ret double %conv
 }
 ; CHECK-LABEL: int64BitcastToDoubleConst
 ; CHECK: mov
 ; ARM32-LABEL: int64BitcastToDoubleConst
 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #57336
 ; ARM32-DAG: movt [[REG0]], #137
 ; ARM32-DAG: movw [[REG1:r[0-9]+]], #0
 ; ARM32-DAG: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]