Chromium Code Reviews
chromiumcodereview-hr@appspot.gserviceaccount.com (chromiumcodereview-hr) | Please choose your nickname with Settings | Help | Chromium Project | Gerrit Changes | Sign out
(31)

Side by Side Diff: tests_lit/llvm2ice_tests/bitcast.ll

Issue 1359193003: Subzero. Enables (most) crosstests for ARM32. (Closed) Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master
Patch Set: Addresses comments. Created 5 years, 2 months ago
Use n/p to move between diff chunks; N/P to move between comments. Draft comments are only viewable by you.
Jump to:
View unified diff | Download patch
« no previous file with comments | « tests_lit/llvm2ice_tests/64bit.pnacl.ll ('k') | tests_lit/llvm2ice_tests/fp.convert.ll » ('j') | no next file with comments »
Toggle Intra-line Diffs ('i') | Expand Comments ('e') | Collapse Comments ('c') | Show Comments Hide Comments ('s')
OLDNEW
1 ; Trivial smoke test of bitcast between integer and FP types. 1 ; Trivial smoke test of bitcast between integer and FP types.
2 2
3 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s 3 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -O2 | FileCheck %s
4 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s 4 ; RUN: %p2i --filetype=obj --disassemble -i %s --args -Om1 | FileCheck %s
5 5
6 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \ 6 ; RUN: %if --need=allow_dump --need=target_ARM32 --command %p2i --filetype=asm \
7 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \ 7 ; RUN: --target arm32 -i %s --args -O2 --skip-unimplemented \
8 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \ 8 ; RUN: | %if --need=allow_dump --need=target_ARM32 --command FileCheck %s \
9 ; RUN: --check-prefix=ARM32 9 ; RUN: --check-prefix=ARM32
10 10
(...skipping 36 matching lines...) Expand 10 before | Expand all | Expand 10 after
47 entry: 47 entry:
48 %v0 = bitcast double 0x12345678901234 to i64 48 %v0 = bitcast double 0x12345678901234 to i64
49 ret i64 %v0 49 ret i64 %v0
50 } 50 }
51 ; CHECK-LABEL: cast_d2ll_const 51 ; CHECK-LABEL: cast_d2ll_const
52 ; CHECK: mov e{{..}},DWORD PTR ds:0x0 {{.*}} .L$double$0 52 ; CHECK: mov e{{..}},DWORD PTR ds:0x0 {{.*}} .L$double$0
53 ; CHECK: mov e{{..}},DWORD PTR ds:0x4 {{.*}} .L$double$0 53 ; CHECK: mov e{{..}},DWORD PTR ds:0x4 {{.*}} .L$double$0
54 ; ARM32-LABEL: cast_d2ll_const 54 ; ARM32-LABEL: cast_d2ll_const
55 ; ARM32-DAG: movw [[ADDR:r[0-9]+]], #:lower16:.L$ 55 ; ARM32-DAG: movw [[ADDR:r[0-9]+]], #:lower16:.L$
56 ; ARM32-DAG: movt [[ADDR]], #:upper16:.L$ 56 ; ARM32-DAG: movt [[ADDR]], #:upper16:.L$
57 ; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]], #0{{\]}} 57 ; ARM32-DAG: vldr [[DREG:d[0-9]+]], {{\[}}[[ADDR]]{{\]}}
58 ; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, [[DREG]] 58 ; ARM32: vmov r{{[0-9]+}}, r{{[0-9]+}}, [[DREG]]
59 59
60 define internal double @cast_ll2d(i64 %ll) { 60 define internal double @cast_ll2d(i64 %ll) {
61 entry: 61 entry:
62 %v0 = bitcast i64 %ll to double 62 %v0 = bitcast i64 %ll to double
63 ret double %v0 63 ret double %v0
64 } 64 }
65 ; CHECK-LABEL: cast_ll2d 65 ; CHECK-LABEL: cast_ll2d
66 ; CHECK: fld QWORD PTR 66 ; CHECK: fld QWORD PTR
67 ; ARM32-LABEL: cast_ll2d 67 ; ARM32-LABEL: cast_ll2d
68 ; ARM32: vmov d{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}} 68 ; ARM32: vmov d{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
69 69
70 define internal double @cast_ll2d_const() { 70 define internal double @cast_ll2d_const() {
71 entry: 71 entry:
72 %v0 = bitcast i64 12345678901234 to double 72 %v0 = bitcast i64 12345678901234 to double
73 ret double %v0 73 ret double %v0
74 } 74 }
75 ; CHECK-LABEL: cast_ll2d_const 75 ; CHECK-LABEL: cast_ll2d_const
76 ; CHECK: mov {{.*}},0x73ce2ff2 76 ; CHECK: mov {{.*}},0x73ce2ff2
77 ; CHECK: mov {{.*}},0xb3a 77 ; CHECK: mov {{.*}},0xb3a
78 ; CHECK: fld QWORD PTR 78 ; CHECK: fld QWORD PTR
79 ; ARM32-LABEL: cast_ll2d_const 79 ; ARM32-LABEL: cast_ll2d_const
80 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #12274 80 ; ARM32-DAG: movw [[REG0:r[0-9]+]], #12274
81 ; ARM32-DAG: movt [[REG0:r[0-9]+]], #29646 81 ; ARM32-DAG: movt [[REG0:r[0-9]+]], #29646
82 ; ARM32-DAG: movw [[REG1:r[0-9]+]], #2874 82 ; ARM32-DAG: movw [[REG1:r[0-9]+]], #2874
83 ; ARM32: vmov d{{[0-9]+}}, [[REG0]], [[REG1]] 83 ; ARM32: vmov d{{[0-9]+}}, [[REG0]], [[REG1]]
OLDNEW
« no previous file with comments | « tests_lit/llvm2ice_tests/64bit.pnacl.ll ('k') | tests_lit/llvm2ice_tests/fp.convert.ll » ('j') | no next file with comments »

Powered by Google App Engine
This is Rietveld 408576698