Subzero. Enables (most) crosstests for ARM32.

tests_lit/llvm2ice_tests/64bit.pnacl.ll

 ; This tries to be a comprehensive test of i64 operations, in
 ; particular the patterns for lowering i64 operations into constituent
 ; i32 operations on x86-32.
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -O2 \
 ; RUN:   | %if --need=target_X8632 --command FileCheck %s
 
 ; RUN: %if --need=target_X8632 --command %p2i --filetype=obj --disassemble \
 ; RUN:   --target x8632 -i %s --args -Om1 \
@@ skipping 73 matching lines @@
 ; OPTM1:      sub     esp
 ; OPTM1:      mov     DWORD PTR [esp+0x4]
 ; OPTM1:      mov     DWORD PTR [esp]
 ; OPTM1:      mov     DWORD PTR [esp+0x8],0x7b
 ; OPTM1:      mov     DWORD PTR [esp+0x10]
 ; OPTM1:      mov     DWORD PTR [esp+0xc]
 ; OPTM1:      call {{.*}} R_{{.*}}    ignore64BitArgNoInline
 
 ; ARM32-LABEL: pass64BitArg
 ; ARM32:      sub     sp, {{.*}} #16
-; ARM32:      str     {{.*}}, [sp, #4]
 ; ARM32:      str     {{.*}}, [sp]
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      add     sp, {{.*}} #16
 ; ARM32:      sub     sp, {{.*}} #16
-; ARM32:      str     {{.*}}, [sp, #4]
 ; ARM32:      str     {{.*}}, [sp]
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      add     sp, {{.*}} #16
 ; ARM32:      sub     sp, {{.*}} #16
-; ARM32:      str     {{.*}}, [sp, #4]
 ; ARM32:      str     {{.*}}, [sp]
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      add     sp, {{.*}} #16
 
 
 declare i32 @ignore64BitArgNoInline(i64, i32, i64)
 
@@ skipping 21 matching lines @@
 ; OPTM1-NEXT: mov     DWORD PTR [esp+0x8],0x7b
 ; Bundle padding might be added (so not using -NEXT).
 ; OPTM1:      mov     DWORD PTR [esp+0x10],0xdeadbeef
 ; OPTM1-NEXT: mov     DWORD PTR [esp+0xc],0x12345678
 ; OPTM1-NOT:  mov
 ; OPTM1:      call {{.*}} R_{{.*}}    ignore64BitArgNoInline
 
 ; ARM32-LABEL: pass64BitConstArg
 ; ARM32:      sub     sp, {{.*}} #16
 ; ARM32:      movw    [[REG1:r.*]], {{.*}} ; 0xbeef
-; ARM32:      movt    [[REG1:r.*]], {{.*}} ; 0xdead
+; ARM32:      movt    [[REG1]], {{.*}}     ; 0xdead
 ; ARM32:      movw    [[REG2:r.*]], {{.*}} ; 0x5678
-; ARM32:      movt    [[REG2:r.*]], {{.*}} ; 0x1234
+; ARM32:      movt    [[REG2]], {{.*}}     ; 0x1234
 ; ARM32:      str     [[REG1]], [sp, #4]
 ; ARM32:      str     [[REG2]], [sp]
 ; ARM32:      {{mov|ldr}} r0
 ; ARM32:      {{mov|ldr}} r1
 ; ARM32:      movw    r2, #123
 ; ARM32:      bl      {{.*}} ignore64BitArgNoInline
 ; ARM32:      add     sp, {{.*}} #16
 
 define internal i32 @pass64BitUndefArg() {
 entry:
@@ skipping 268 matching lines @@
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shl64BitSigned
 ; OPTM1: shld
 ; OPTM1: shl e
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
 ; ARM32-LABEL: shl64BitSigned
-; ARM32: sub [[REG3:r.*]], [[REG2:r.*]], #32
-; ARM32: lsl [[REG1:r.*]], {{r.*}}, [[REG2]]
-; ARM32: orr [[REG1]], [[REG1]], [[REG0:r.*]], lsl [[REG3]]
-; ARM32: rsb [[REG4:r.*]], [[REG2]], #32
-; ARM32: orr [[REG1]], [[REG1]], [[REG0]], lsr [[REG4]]
-; ARM32: lsl {{.*}}, [[REG0]], [[REG2]]
+; ARM32: rsb     [[T0:r[0-9]+]], r2, #32
+; ARM32: lsr     [[T1:r[0-9]+]], r0, [[T0]]
+; ARM32: orr     [[T2:r[0-9]+]], [[T1]], r1, lsl r2
+; ARM32: sub     [[T3:r[0-9]+]], r2, #32
+; ARM32: cmp     [[T3]], #0
+; ARM32: lslge   [[T2]], r0, [[T3]]
+; ARM32: lsl     r{{[0-9]+}}, r0, r2
 
 define internal i32 @shl64BitSignedTrunc(i64 %a, i64 %b) {
 entry:
   %shl = shl i64 %a, %b
   %result = trunc i64 %shl to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shl64BitSignedTrunc
 ; CHECK: mov
 ; CHECK: shl e
@@ skipping 20 matching lines @@
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shl64BitUnsigned
 ; OPTM1: shld
 ; OPTM1: shl e
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
 ; ARM32-LABEL: shl64BitUnsigned
+; ARM32: rsb
+; ARM32: lsr
+; ARM32: orr
 ; ARM32: sub
-; ARM32: lsl
-; ARM32: orr
-; ARM32: rsb
-; ARM32: orr
+; ARM32: cmp
+; ARM32: lslge
 ; ARM32: lsl
 
 define internal i64 @shr64BitSigned(i64 %a, i64 %b) {
 entry:
   %shr = ashr i64 %a, %b
   ret i64 %shr
 }
 ; CHECK-LABEL: shr64BitSigned
 ; CHECK: shrd
 ; CHECK: sar
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ; CHECK: sar {{.*}},0x1f
 ;
 ; OPTM1-LABEL: shr64BitSigned
 ; OPTM1: shrd
 ; OPTM1: sar
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: shr64BitSigned
-; ARM32: rsb
-; ARM32: lsr
-; ARM32: orr
-; ARM32: subs
-; ARM32: orrpl
-; ARM32: asr
+; ARM32: lsr     [[T0:r[0-9]+]], r0, r2
+; ARM32: rsb     [[T1:r[0-9]+]], r2, #32
+; ARM32: orr     r0, [[T0]], r1, lsl [[T1]]
+; ARM32: sub     [[T2:r[0-9]+]], r2, #32
+; ARM32: cmp     [[T2]], #0
+; ARM32: asrge   r0, r1, [[T2]] 
+; ARM32: asr     r{{[0-9]+}}, r1, r2
 
 define internal i32 @shr64BitSignedTrunc(i64 %a, i64 %b) {
 entry:
   %shr = ashr i64 %a, %b
   %result = trunc i64 %shr to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shr64BitSignedTrunc
 ; CHECK: shrd
 ; CHECK: sar
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shr64BitSignedTrunc
 ; OPTM1: shrd
 ; OPTM1: sar
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 ; OPTM1: sar {{.*}},0x1f
 
 ; ARM32-LABEL: shr64BitSignedTrunc
+; ARM32: lsr
 ; ARM32: rsb
-; ARM32: lsr
 ; ARM32: orr
-; ARM32: subs
-; ARM32: orrpl
+; ARM32: sub
+; ARM32: cmp
+; ARM32: asrge
 
 define internal i64 @shr64BitUnsigned(i64 %a, i64 %b) {
 entry:
   %shr = lshr i64 %a, %b
   ret i64 %shr
 }
 ; CHECK-LABEL: shr64BitUnsigned
 ; CHECK: shrd
 ; CHECK: shr
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shr64BitUnsigned
 ; OPTM1: shrd
 ; OPTM1: shr
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
 ; ARM32-LABEL: shr64BitUnsigned
+; ARM32: lsr
 ; ARM32: rsb
-; ARM32: lsr
 ; ARM32: orr
 ; ARM32: sub
-; ARM32: orr
+; ARM32: cmp
+; ARM32: lsrge
 ; ARM32: lsr
 
 define internal i32 @shr64BitUnsignedTrunc(i64 %a, i64 %b) {
 entry:
   %shr = lshr i64 %a, %b
   %result = trunc i64 %shr to i32
   ret i32 %result
 }
 ; CHECK-LABEL: shr64BitUnsignedTrunc
 ; CHECK: shrd
 ; CHECK: shr
 ; CHECK: test {{.*}},0x20
 ; CHECK: je
 ;
 ; OPTM1-LABEL: shr64BitUnsignedTrunc
 ; OPTM1: shrd
 ; OPTM1: shr
 ; OPTM1: test {{.*}},0x20
 ; OPTM1: je
 
 ; ARM32-LABEL: shr64BitUnsignedTrunc
+; ARM32: lsr
 ; ARM32: rsb
-; ARM32: lsr
 ; ARM32: orr
 ; ARM32: sub
-; ARM32: orr
+; ARM32: cmp
+; ARM32: lsrge
 
 define internal i64 @and64BitSigned(i64 %a, i64 %b) {
 entry:
   %and = and i64 %b, %a
   ret i64 %and
 }
 ; CHECK-LABEL: and64BitSigned
 ; CHECK: and
 ; CHECK: and
 ;
@@ skipping 1199 matching lines @@
 ; CHECK-LABEL: phi64Undef
 ; CHECK: mov {{.*}},0x0
 ; CHECK: mov {{.*}},0x0
 ; OPTM1-LABEL: phi64Undef
 ; OPTM1: mov {{.*}},0x0
 ; OPTM1: mov {{.*}},0x0
 ; ARM32-LABEL: phi64Undef
 ; ARM32: mov {{.*}} #0
 ; ARM32: mov {{.*}} #0