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| 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// | 1 //===- subzero/src/IceInstARM32.def - X-Macros for ARM32 insts --*- C++ -*-===// |
| 2 // | 2 // |
| 3 // The Subzero Code Generator | 3 // The Subzero Code Generator |
| 4 // | 4 // |
| 5 // This file is distributed under the University of Illinois Open Source | 5 // This file is distributed under the University of Illinois Open Source |
| 6 // License. See LICENSE.TXT for details. | 6 // License. See LICENSE.TXT for details. |
| 7 // | 7 // |
| 8 //===----------------------------------------------------------------------===// | 8 //===----------------------------------------------------------------------===// |
| 9 // | 9 // |
| 10 // This file defines properties of ARM32 instructions in the form of x-macros. | 10 // This file defines properties of ARM32 instructions in the form of x-macros. |
| (...skipping 332 matching lines...) Expand 10 before | Expand all | Expand 10 after Loading... |
| 343 X(Reg_DREG_First, = Reg_d0) \ | 343 X(Reg_DREG_First, = Reg_d0) \ |
| 344 X(Reg_DREG_Last, = Reg_d31) \ | 344 X(Reg_DREG_Last, = Reg_d31) \ |
| 345 X(Reg_QREG_First, = Reg_q0) \ | 345 X(Reg_QREG_First, = Reg_q0) \ |
| 346 X(Reg_QREG_Last, = Reg_q15) | 346 X(Reg_QREG_Last, = Reg_q15) |
| 347 // define X(val, init) | 347 // define X(val, init) |
| 348 | 348 |
| 349 // Load/Store instruction width suffixes and FP/Vector element size suffixes | 349 // Load/Store instruction width suffixes and FP/Vector element size suffixes |
| 350 // the # of offset bits allowed as part of an addressing mode (for sign or zero | 350 // the # of offset bits allowed as part of an addressing mode (for sign or zero |
| 351 // extending load/stores). | 351 // extending load/stores). |
| 352 #define ICETYPEARM32_TABLE \ | 352 #define ICETYPEARM32_TABLE \ |
| 353 /* tag, element type, int_width, vec_width, addr bits sext, zext */ \ | 353 /* tag, element type, int_width, vec_width, addr bits sext, zext, \ |
| 354 X(IceType_void, IceType_void, "" , "" , 0 , 0) \ | 354 reg-reg addr allowed */ \ |
| 355 X(IceType_i1, IceType_void, "b", "" , 8 , 12) \ | 355 X(IceType_void, IceType_void, "" , "" , 0 , 0 , 0) \ |
| 356 X(IceType_i8, IceType_void, "b", "" , 8 , 12) \ | 356 X(IceType_i1, IceType_void, "b", "" , 8 , 12, 1) \ |
| 357 X(IceType_i16, IceType_void, "h", "" , 8 , 8) \ | 357 X(IceType_i8, IceType_void, "b", "" , 8 , 12, 1) \ |
| 358 X(IceType_i32, IceType_void, "" , "" , 12, 12) \ | 358 X(IceType_i16, IceType_void, "h", "" , 8 , 8 , 1) \ |
| 359 X(IceType_i64, IceType_void, "d", "" , 8 , 8) \ | 359 X(IceType_i32, IceType_void, "" , "" , 12, 12, 1) \ |
| 360 X(IceType_f32, IceType_void, "" , ".f32", 10, 10) \ | 360 X(IceType_i64, IceType_void, "d", "" , 8 , 8 , 1) \ |
| 361 X(IceType_f64, IceType_void, "" , ".f64", 10, 10) \ | 361 X(IceType_f32, IceType_void, "" , ".f32", 8, 8 , 0) \ |
| 362 X(IceType_v4i1, IceType_i32 , "" , ".i32", 0 , 0) \ | 362 X(IceType_f64, IceType_void, "" , ".f64", 8, 8 , 0) \ |
| 363 X(IceType_v8i1, IceType_i16 , "" , ".i16", 0 , 0) \ | 363 X(IceType_v4i1, IceType_i32 , "" , ".i32", 0 , 0 , 1) \ |
| 364 X(IceType_v16i1, IceType_i8 , "" , ".i8" , 0 , 0) \ | 364 X(IceType_v8i1, IceType_i16 , "" , ".i16", 0 , 0 , 1) \ |
| 365 X(IceType_v16i8, IceType_i8 , "" , ".i8" , 0 , 0) \ | 365 X(IceType_v16i1, IceType_i8 , "" , ".i8" , 0 , 0 , 1) \ |
| 366 X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0) \ | 366 X(IceType_v16i8, IceType_i8 , "" , ".i8" , 0 , 0 , 1) \ |
| 367 X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0) \ | 367 X(IceType_v8i16, IceType_i16 , "" , ".i16", 0 , 0 , 1) \ |
| 368 X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0) | 368 X(IceType_v4i32, IceType_i32 , "" , ".i32", 0 , 0 , 1) \ |
| 369 //#define X(tag, elementty, int_width, vec_width, sbits, ubits) | 369 X(IceType_v4f32, IceType_f32 , "" , ".f32", 0 , 0 , 1) |
| 370 //#define X(tag, elementty, int_width, vec_width, sbits, ubits, rraddr) |
| 370 | 371 |
| 371 // Shifter types for Data-processing operands as defined in section A5.1.2. | 372 // Shifter types for Data-processing operands as defined in section A5.1.2. |
| 372 #define ICEINSTARM32SHIFT_TABLE \ | 373 #define ICEINSTARM32SHIFT_TABLE \ |
| 373 /* enum value, emit */ \ | 374 /* enum value, emit */ \ |
| 374 X(LSL, "lsl") \ | 375 X(LSL, "lsl") \ |
| 375 X(LSR, "lsr") \ | 376 X(LSR, "lsr") \ |
| 376 X(ASR, "asr") \ | 377 X(ASR, "asr") \ |
| 377 X(ROR, "ror") \ | 378 X(ROR, "ror") \ |
| 378 X(RRX, "rrx") | 379 X(RRX, "rrx") |
| 379 //#define X(tag, emit) | 380 //#define X(tag, emit) |
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| 395 X(LS, 9 , HI, "ls") /* unsigned lower or same */ \ | 396 X(LS, 9 , HI, "ls") /* unsigned lower or same */ \ |
| 396 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ | 397 X(GE, 10, LT, "ge") /* signed greater than or equal */ \ |
| 397 X(LT, 11, GE, "lt") /* signed less than */ \ | 398 X(LT, 11, GE, "lt") /* signed less than */ \ |
| 398 X(GT, 12, LE, "gt") /* signed greater than */ \ | 399 X(GT, 12, LE, "gt") /* signed greater than */ \ |
| 399 X(LE, 13, GT, "le") /* signed less than or equal */ \ | 400 X(LE, 13, GT, "le") /* signed less than or equal */ \ |
| 400 X(AL, 14, kNone, "") /* always (unconditional) */ \ | 401 X(AL, 14, kNone, "") /* always (unconditional) */ \ |
| 401 X(kNone, 15, kNone, "??") /* special condition / none */ | 402 X(kNone, 15, kNone, "??") /* special condition / none */ |
| 402 //#define(tag, encode, opp, emit) | 403 //#define(tag, encode, opp, emit) |
| 403 | 404 |
| 404 #endif // SUBZERO_SRC_ICEINSTARM32_DEF | 405 #endif // SUBZERO_SRC_ICEINSTARM32_DEF |
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Chromium Code Reviews
Issue 1359193003:
Subzero. Enables (most) crosstests for ARM32. (Closed)
Base URL: https://chromium.googlesource.com/native_client/pnacl-subzero.git@master